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Vivado Lab6 FPGA done bit not gone high

Former Member

Hi,
I am facing a problem, I was doing the speedy way Vavodo labs on my newly got Zedboard. Smoothly I reached to Lab 6. but here i am stuck. I am not able to program FPGA. This step is just before the lab Run configuration my application. When i click the FPGA program button, an error is poped up and saying that FPGA could not program, done bit did not go high. I made sure that the board is in the cascaded JTAG program and digilent usb-jatg drivers are installed properly.
Pls help.

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    Hi Praveenlal,

    If you have already verified that jumpers JP7 to JP11 have been set to JTAG mode and you have been able to download software applications to the target and execute correctly, then it sounds like your download cable and JTAG chain is intact.

    The other common cause of this problem that I have seen is that in earlier labs, the wrong Zynq device is selected and so the bitstream file generated does not match the target device on ZedBoard.  Please verify that your Vivado Block Design uses a xc7Z020clg484-1 target device.

    Regards,

    -Kevin

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  • 0

    Hi Praveenlal,

    If you have already verified that jumpers JP7 to JP11 have been set to JTAG mode and you have been able to download software applications to the target and execute correctly, then it sounds like your download cable and JTAG chain is intact.

    The other common cause of this problem that I have seen is that in earlier labs, the wrong Zynq device is selected and so the bitstream file generated does not match the target device on ZedBoard.  Please verify that your Vivado Block Design uses a xc7Z020clg484-1 target device.

    Regards,

    -Kevin

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