Having gone through the SDR labs that are currently posted, there is mention of the timing recovery being implemented using HDL coder in a later lab.
There is clearly a lab4 folder (and indeed solution) but no lab4 document is included.
Is this going to be made available at some point in the near future?
Thanks,
Iain
The instructions for Lab 4 of the older SDR Speedway were never finalized, so there is nothing to find.
You might want to take a look at the newer SDR-II Design Seminar material:
Integrated Software-Defined Radio on Zynq
-7000 All Programmable SoC
While the symbol timing recovery design is different, the instructions and demo might be useful.
-Gary
