Hello there!
I have some issues with one Lab in the HLS Tutorial (UG871, v 2013.2, June 19, 2013). It is the Lab #2 in "Using HLS IP in a Zynq Processor Design". In this lab a high speed connection between CPU memory and PL is made.
I can go through every step and even compile the code. But when i run the code, it gets stuck on a loop, because the DMA is always busy. Is there somebody that was able to do this on the zedboard?
Thank you very much!