About ZedBoard's SD card interface

I am making a PS configration of ZED by ISE 14.1. For SD card interface, the HW User's Guide and the schematic both use MIO[40..47] . But in XPS tools, only find MIO[40..45] when enable SD0. The MIO[46..47] are used for UART0. Why?

BTW, about zynq chip model,HW user's Guide is XC7Z020-1CSG484.However, Schematic is XC7Z020-1CLG484. Any difference?

Fermi

0 Former Member over 13 years ago

Fermi,

Xilinx moved to the CLG package for better signal integrity. The Users Guide was written before the change. I will pass along the recommendation to change it.
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0 Former Member over 13 years ago

In my XPS tools, I find MIO[40...47] are use for SD0.Do you use the ZC702 Development Board Template?
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0 bhfletcher over 13 years ago

Fermi,
There are 6 primary SD connections, which is what you see with MIO[40:45]. If you click the + (plus) sign in front of the SD peripheral, you'll find optional connections for WP, CD, and Power. On ZedBoard, we connect WP to MIO[46] and CD to MIO[47]. Note that the location of the primary and optional connections all have some flexibility.
ZC702 uses the same MIO[40:45] for the primary connections, but CD is connected to MIO[0] and WP is at MIO[15].
I found one additional stray reference to the CSG package in the HW UG (on Figure 1 Block Diagram). We are using the CLG package and will get this typo corrected soon.
Bryan
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0 Former Member over 13 years ago in reply to Former Member

minm,

You may find this blog post helpful:

http://zynqgeek.blogspot.com/2012/08/zedboard-create-planahead-project-with.html
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