Can I use AFE7444EVM (JESD204B) with PicoZed FMC Carrier V2?

Hi there,

1 - You'll have to validate the schematic against the PicoZed Carrier Schematic to ensure that the needs of the FMC Card are met

2 - The PicoZed can do FFTS, like any FPGA device.  Which is faster?  It depends on what you are trying to accomplish / do and your skill level as well as what tools you are using

3 - As mentioned above, you do not provide enough information for anyone to take more than a guess about if it is fast enough, nor information about your skill level regarding being able to manipulate the FPGA HDL to bend it to your needs

As mentioned above, what are you doing?

--Dan

Hi Dan,

Thanks very much for the response and sorry for missing out a few relevant details. First of all, I have zero experience with FPGA HDL, so the easiest solution to implement is probably the best. I can probably learn the basics, though.

Below I'll try to very briefly describe what I am trying to do. For more details, there is a recent scientific paper reporting a very similar system, but with a slower ADC (Torjesen et al. Journal of Biomedical Optics 2017).

In my system, I will use a DDS chip to modulate up to eight lasers at several different frequencies between 50 and 400 MHz (between 5 and 50 MHz steps). At each step, I will simultaneously modulated each of the eight different lasers with a slightly different frequency (>20 MHz difference). After shining these lasers to a sample, I'll use an APD to monitor the light intensity changes. It should be possible to see each of the eight different frequency peaks in the frequency spectrum of the APD signal. The whole process will be controlled by a Labview or Python software in a host computer.

What I need from the PicoZed board + ADC (the reason for the question) is to compute the FFT amplitude and phase at each of the 8 different frequencies, for each modulation modulation step (FFT with >4096 points). I need the ADC to acquire data with at least 1.2 Gsps, and I will need to compute between 7 and 70 FFTs, dedepening on the step size of the frequency sweeps (the step size will change depending on the application).

In my application, I need to compute the FFT for all the different modulation steps in less than 100 ms (faster is better), and then store the amplitude and phase values of the relevant frequencies in a computer (a set of vectors with size # of steps x 8).

Please let me know if this clarify your questions.

PS: I will try to check the FCM board requirements and compare with the carrier card schematic. Thanks.

EDIT: I'll have to compute the FFT from three different sources (2 APDs + 1 reference signal). This is not going to be part of the initial testing, but it should be in the final prototype.

Hi there,

Ok, once you know the board will physically work, you should get the Vivado tools and decide if you want to use SDSoC or not.  If you have zero experience in HDL, you will either need to learn it and model your FFT/etc. so you can determine if it will work in the timeframe you need - if not modify it, or use some built in / purchased IP, or you can try to use SDSoC and model that way.

Do you have a local FAE you are working with?

--Dan

Hi Dan,

Unfortunately, I don't have a local FAE for this. That's why I came here to get some guidance.

Thanks very much for your tips! It's already very helpful!

One thing that everyone finds challenging is Implementing the JESD204B protocol. Xilinx offers a pay-for IP core (link), but implementing it in a system takes some expertise.

You might want to consider using the Xilinx ZCU111 evalution board, which has their UltraScale+ RFSoC device. You can do 8 channels 12-bit ADC @ 4Gsps and 8 channels 14-bit DAC at 6.544Gsps (instantaneous analog BW for both is 4GHz). The advantage there is that the converters hook natively into the programmable logic - no JESD204B mess. You'll probably want to add this SMA daughtercard as well.

Depending on your timeline, you may want to either hire a consultant or sign up for training. Honestly, people make a living knowing how to connect gigasample converters to FPGAs and do all the high-speed signal processing on the back end.  Beyond HDL knowledge, you'll need experience in making tradeoffs between resource utilization vs. speed, closing timing, debugging algorithms, improving throughput, the list goes on.

Best of luck. Sounds like a very interesting project!

/Matt

Thank you very much four your suggestions.

I will try to find someone with more expertise with FPGA development at my University, and maybe I'll have to go with the more expensive solution you suggested. It looks like an overkill for my purpose, but it definitely looks like it will be a lot easier to work with.

I really appreciate all the help!

Thank you very much four your suggestions.

I will try to find someone with more expertise with FPGA development at my University, and maybe I'll have to go with the more expensive solution you suggested. It looks like an overkill for my purpose, but it definitely looks like it will be a lot easier to work with.

I really appreciate all the help!