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MaaxBoard-RT: two SPI = DualSPIder - works

tjaekel

I found a second SPI on J1 header.
So, I have now implemented the "DualSPIder".

What is DualSPIder?

It is used to compensate "Round Trip Delays":
A SPI Master will send (SCLK, MOSI, CS) but the MISO signal from far end (DUT, "Device Under Test") is delayed (e.g. due to ribbon cable or additional line drivers, or using LVDS...).
So, the SCLK is "mirrored back" at the far end (affected by the same delay due to cable length and drivers) and SCLK', MISO are going into a SPI Slave (still as "synchronous").
So, it compensates the "round trip delay", or the additional delays due to line driver, LVDS interfaces...

DualSPIder approach

Figure 1: DualSPIder approach

One SPI Master and one SPI Slave: the slave receives the "mirrored" SCLK signal so that MISO and SCL are still in sync on MCU receiver (SPI is synchronous!),
never mind how long the cable is; if additional drivers are there or if we use LVDS logic (and converters on both end) - the delay is compensated by this approach.

Changed J1 pin usage

In order to gain the second SPI (LPSPI2) I had to free the Debug UART as LPUART1.
Debug UART is now LPUART6 (see the other pins on J1 and connect to it with your MCU-LINK!).

Testing SPI

if you want to test the SPI via Loopback - to see on Rx what was sent on Tx - you had to use now three wires:

J1, pin 21 - to J1, pin 31
J1, pin 23 - to J1, pin 8
J1, pin 24 - to J1, pin 10

All what you send should also be received (and reported on USB VCP UART).

J1 pin usage

Figure 2: "my" J1 pin usage for DualSPIder and for future use

SPI Performance

I have tested how fast I can go (with this SPI Master plus SPI Slave approach).
ATT: the clock config is modified, in order to increase the speed on SPI: default was just 12 Mbps/MHz.

I can reach:

55.6 MHz for this Master + Slave combination is the maximum I could achieve.
(anyway: way better as the Teensy 4.1 board!)
I use a bit slower: 45.4 MHz, which results in a minimum speed of 4 KHz.

The project is here:

tjaekel/MaaXBoard-RT_SPIder: MaaXBoard-RT SPIder framework (github.com)

  • BTW:
    We do not need this PCS0 signal on the SPI Slave, acting as the Slave Rx.
    The "beauty" is:

    • it gains one additional GPIO
    • I have a "shared SPI bus": two slaves with two PCSx signals selected, responding on the same MISO signal
    • using both Slave PCS0 and PCS1 as a HW signals as PCS0 on Slave: I had to combine via an AND gate: either slave can be addressed and
      therefore my SPI Slave Rx has to be selected with either one of the PCSx signals
      (I can save external logic)

    The "trick" is:

    The MCU LPSPI has an AUTOPCS feature:
    You can run a Slave Rx without a PCS, just SCLK and MISO.
    See in Reference Manual, page 5561, paragraph "70.3.2.3 Clocked interface".

    So, it comes to this approach:

    DualSPIder with Slave Rx AUTOPCS

    Remark:
    This AUTOPCS is not supported by the SDK drivers (file: "fsl_lpspi.c"):
    the macro for setting this bit is defined as: LPSPI_CFGR1_AUTOPCS(1)
    but it is never used.

    I have added this line of code in file "fsl_lpspi.c":

    //XXXX: no need for PCS0 on SPI Slave - we use PCS polarity High as indication
    if (slaveConfig->pcsActiveHighOrLow == kLPSPI_PcsActiveHigh)
        base->CFGR1 = base->CFGR1 | LPSPI_CFGR1_AUTOPCS(1);

    So, when I set the logic level for the PCS signal as HIGH (usually it is LOW), I set also this AUTOPCS bit.
    Just to make sure to set also the other requirements, e.g. CPHA = 1.
    See this excerpt from Reference Manual:

    AUTOPCS manual statement

  • in reply to tjaekel

    Interesting, I have not spotted that feature on a  micro before.

    MK

  • in reply to michaelkellett

    BTW: it works a bit similar on an STM32 MCUs:
    if you configure a SPI slave, you can do without to use a HW input signal for Slave Select (nSS, or nCS).
    The STM32 MCU allows to enable/disable a SPI slave also via a SW bit set or unset, when you are ready enable the slave.

    Here, I guess (not tried): the PCSPOL[0] might work in a similar way: if 1 - Slave is enabled, if 0 - Slave is disabled
    (would not receive, e.g. garbage, so, a slave could be in sync with a SPI Tx Master (just active when also sending))

  • in reply to tjaekel

    Actually it was the clock syncing I hadn't seen before.

    MK