I could implement the QSPI on the available header pins also via FLEXIO2 (instead of "FastGPIO").
It works (at least the QSPI write waveform looks correct).
The project is here:
Is uses FLEXIO2 pins and FLEXIO2 to generate the 4 bit parallel QSPI data lanes.
It works up to 30 MHz, 60 MHz might have a bit "strange" waveform.
The project is still under development - I need to add QSPI read
(change the pin direction, but similar approach).
It has modified SDK drivers !!, e.g. "fsl_flexio_spi.c": I have 'hijacked' the FLEXIO SPI drivers for it
(see the macro "FLEXIO_QSPI" added).
I had to modify the shifter configuration, esp. the WIDTH and the TIMER for the SCLK signal,