I have been looking at the microzed design as well as the carrier board schematics that has been recently released. I have so far found that within the carrier card schematics, pins 48&50 of the JX2 FCI header has seemingly inputs for clocks. So my questions are the following;
1) Are there only two pins on both FCI connectors one can use as clock lines into the FPGA? (Thus connected to the global clock buffer). In the hardware guide there is mention of more, but the pins on the FCI connector is not stated.
2) What does the BB in the BB_CLK and BB_CLK_EN net assignments for pins 48&50 on the JX2 header stand for?
Any insight would be appreciated.