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global clock pins

Former Member

Hi All,

I have been looking at the microzed design as well as the carrier board schematics that has been recently released. I have so far found that within the carrier card schematics, pins 48&50 of the JX2 FCI header has seemingly inputs for clocks. So my questions are the following;

1) Are there only two pins on both FCI connectors one can use as clock lines into the FPGA? (Thus connected to the global clock buffer). In the hardware guide there is mention of more, but the pins on the FCI connector is not stated.

2) What does the BB in the BB_CLK and BB_CLK_EN net assignments for pins 48&50 on the JX2 header stand for?

Any insight would be appreciated.

Regards

  • 0

    BB stands for Base Board. BB_CLK on the IO Carrier is the output of a 100 MHz oscillator. BB_CLK_EN is a logical signal attached to the Enable pin of the 100 MHz oscillator.

     

    BB_CLK is attached to JX2.pin48. That mating pin on the MicroZed is tied to signal JX2_LVDS_11_P, which is tied to pin K17 on the Zynq, which is Zynq pin IO_L12P_T1_MRCC_35. MRCC is Multi-region clock capable. SRCC is Single-region clock capable. You can get more details on this in UG472 and UG865.

     

    If you scroll through the MicroZed pinout, you'll see that the microheaders give you access to:

    •   Two MRCC pairs each on JX1/JX2 (four total)  
          
      •     JX1_LVDS_11_P/N [JX1.42/44] -- LEDs on IOCC
        •   
      •     JX1_LVDS_12_P/N [JX1.47/49] -- Pmod JC on IOCC
        •   
      •     JX2_LVDS_11_P/N [JX2.48/50] -- 100 MHz single-ended clock on IOCC
        •   
      •     JX2_LVDS_12_P/N [JX2.53/55] -- Pmod JG on IOCC
        •  
    •   Two SRCC pairs each on JX1/JX2 (four total)  
          
      •     JX1_LVDS_10_P/N [JX1.41/43] -- LEDs on IOCC
        •   
      •     JX1_LVDS_13_P/N [JX1.48/50] -- Pmod JC on IOCC
        •   
      •     JX2_LVDS_10_P/N [JX2.47/49] -- XADC on IOCC
        •   
      •     JX2_LVDS_13_P/N [JX2.54/56] -- Pmod JG on IOCC
        •  

    That's 8 clocks that you have access to through the microheaders. On the IOCC you get the 100 MHz single-ended clock. Otherwise, you have access to four more clocks through Pmods JC and JG on the IOCC.

     

    Bryan