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Novice with Zynq DDR3 Memory Controller ...

Former Member

Hi, sorry for my poor english.

I am a beginner with DDR3, I have just finished creating a custom PCB that use
Zynq 7010 by referring to the PCB of MicroZed card with two DDR3 memory Fly-By
configuration.

Before starting to work on my PCB, I documented as much as possible, I have read
the guidelines provided by Xilinx with exploring Gerber files of MicroZed card.
I also checked the settings in the tool as Vivado inquiries concerning the
memory available on the controller chipo Zynq 7010, but I have noticed several
inconsistencies.

This is the hardware configuration of my board, practically equal to MicroZed
used as a reference.

################################################################################
# MicroZed Fly-by Hardware Configuration                                       #
#                                                                              #
# DDR_0 (data 15:0)  (longer path)                                             #
# DDR_1 (data 31:16) (shortest path)                                           #
################################################################################

Zynq ADDR       ------> DDR_1 ------> DDR_0 ------> Termination
Zynq BAtt------> DDR_1 ------> DDR_0 ------> Termination
Zynq CASt------> DDR_1 ------> DDR_0 ------> Termination
Zynq RASt------> DDR_1 ------> DDR_0 ------> Termination
Zynq CKE t------> DDR_1 ------> DDR_0 ------> Termination
Zynq CS t------> DDR_1 ------> DDR_0 ------> Termination
Zynq ODTt------> DDR_1 ------> DDR_0 ------> Termination
Zynq RSTt------> DDR_1 ------> DDR_0 ------> Termination
Zynq WEtt------> DDR_1 ------> DDR_0 ------> Termination

Zynq CLK t------> DDR_1 ------> DDR_0 ------> Termination

Zynq DQS0t--------------------> DDR_0
Zynq DQS1t--------------------> DDR_0

Zynq DM0    t--------------------> DDR_0
Zynq DM1    t--------------------> DDR_0

Zynq DQ[0:7]t--------------------> DDR_0
Zynq DQ[8:15]t--------------------> DDR_0

Zynq DQS2    t------> DDR_1
Zynq DQS3    t------> DDR_1

Zynq DQ[16:23] t------> DDR_1
Zynq DQ[24:31] t------> DDR_1

Zynq DM2    t------> DDR_1
Zynq DM3    t------> DDR_1

I extracted the flight times with regard to the chip Zynq 7010:

################################################################################
# MicroZed (xc7z010clg400-1) Package Delay (ps)                                #
################################################################################

# PINttttpsttmm (160 ps/inch) (6.29921 ps/mm)
----------------------------------------------------------------------
DDR_CLOCK_0_PS_DELAY  tt54.536tt8.6576
DDR_CLOCK_1_PS_DELAY tt54.536tt8.6576
DDR_CLOCK_2_PS_DELAYtt54.536tt8.6576
DDR_CLOCK_3_PS_DELAYtt54.536tt8.6576
DDR_DQS_0_PS_DELAYtt101.239tt16.0717tt
DDR_DQS_1_PS_DELAYtt79.5025tt12.6210
DDR_DQS_2_PS_DELAYtt60.536tt9.6101
DDR_DQS_3_PS_DELAYtt71.7715tt11.3937
DDR_DQ_0_[0:7]_PS_DELAYtt104.5365t16.5951
DDR_DQ_1_[8:15]_PS_DELAY    t70.676tt11.2198
DDR_DQ_2_[16:23]_PS_DELAYt59.1615tt9.3919
DDR_DQ_3_[24:31]_PS_DELAY t81.319tt12.909

This are the lengths of the MicroZed slopes:

################################################################################
# MicroZed (xc7z010clg400-1) PCB Trace Length                                  #
################################################################################

# PINttttpsttmm (160 ps/inch) (6.29921 ps/mm)
----------------------------------------------------------------------
DDR_CLOCK_0_PS_DELAYtt341.1058t54.15057
DDR_CLOCK_1_PS_DELAYtt341.1058t54.15057tt
DDR_CLOCK_2_PS_DELAYtt249.5747t39.62000
DDR_CLOCK_3_PS_DELAYtt249.5747t39.62000
DDR_DQS_0_PS_DELAYtt315.2665t50.04858
DDR_DQS_1_PS_DELAYtt317.6282t50.42350
DDR_DQS_2_PS_DELAYtt315.6051t50.10233
DDR_DQS_3_PS_DELAYtt314.9792t50.00297
DDR_DQ_0_[0:7]_PS_DELAYtt312.3698t49.58869
DDR_DQ_1_[8:15]_PS_DELAYt325.8481t51.72840
DDR_DQ_2_[16:23]_PS_DELAYt316.8900t50.30503
DDR_DQ_3_[24:31]_PS_DELAYt305.8200t48.54893

This are the flight times + the lengths of the MicroZed slopes:

################################################################################
# MicroZed (xc7z010clg400-1) Package Delay + PCB Trace Length (ps)             #
################################################################################

# PINttttpsttmm (160 ps/inch) (6.29921 ps/mm)
----------------------------------------------------------------------
DDR_CLOCK_0_PS_DELAYtt395.6418t62.8082
DDR_CLOCK_1_PS_DELAYtt395.6418t62.8082
DDR_CLOCK_2_PS_DELAYtt304.1107t48.2776
DDR_CLOCK_3_PS_DELAYtt304.1107t48.2776t
DDR_DQS_0_PS_DELAYtt416.5055        66.1208
DDR_DQS_1_PS_DELAYtt397.1307t63.0445
DDR_DQS_2_PS_DELAYtt376.1411t59.7124
DDR_DQS_3_PS_DELAYtt387.7507t61.5554
DDR_DQ_0_[0:7]_PS_DELAYtt416.9063t66.1839
DDR_DQ_1_[8:15]_PS_DELAYt396.5241t62.9482
DDR_DQ_2_[16:23]_PS_DELAYt376.0515t59.6982
DDR_DQ_3_[24:31]_PS_DELAYt387.1390t61.4583

Searching through all available files for MicroZed I could find these "data"
that confirm my measurements:

################################################################################
# MicroZed Config                                                              #
################################################################################

CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM t{39.7}tt
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM t{39.7}
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM t{54.14}
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM t{54.14}
CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM tt{50.05}
CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM tt{50.43}
CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM tt{50.10}
CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM tt{50.01}
CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM tt{49.59}
CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM tt{51.74}
CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM tt{50.32}
CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM tt{48.55}

I noticed a discrepancy with respect to my measurements only on the clock, it
seems that the clock is inverted 0-1 with the clock 2-3, maybe it's just an
error.

The MicroZed hardware configuration for the clock:

Zynq CLK ----------> DDR_1 ----------> DDR_0
          39.70 mm          14.44 mmtt
t |                           |
t -------- 54.14 mm ---------/

Why the clock 0 and 1 are used to DDR_1 and not for DDR_0? Should not be the
opposite ?

With these values the Vivado tool (2016.01) calculates the values automatically:

CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 t{-0.112}
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 t{-0.093}
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 t{0.019}
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 t{0.009}
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 tt{0.361}
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 tt{0.351}
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 tt{0.386}
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 tt{0.391}

See: http://s33.postimg.org/5xnfiwrcf/Micro_Zed_Calculated_DDR3_Memory_Controller_Timin.png

The Vivado tool (2016.01) reports an error for the "-0.112" value, the minimum
admitted is "-0.100". Bringing back the clock values as they should be the error
is resolved:

CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM t{54.14}tt
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM t{54.14}
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM t{39.7}
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM t{39.7}
CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM tt{50.05}
CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM tt{50.43}
CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM tt{50.10}
CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM tt{50.01}
CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM tt{49.59}
CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM tt{51.74}
CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM tt{50.32}
CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM tt{48.55}

New valid value calculate by Vivado (2016.01):

CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 t{-0.021}tt
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 t{-0.002}
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 t{-0.071}
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 t{-0.082}
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 tt{0.406}
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 tt{0.396}
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 tt{0.340}
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 tt{0.346}

See : http://s33.postimg.org/o5yyrrwj3/Micro_Zed_Calculated_Corrected_DDR3_Memory_Contro.png

All calculated values with the parameters entered by the circuit extracts
printed, they are correct and valid.

It, however, has another problem: why the entered values are not the same input
using the "User Input" mode? From whence come the values entered manually ? The
values are significantly different from those calculated with the tool, how is
it possible ?

See : http://s33.postimg.org/le6yt206n/Micro_Zed_User_DDR3_Memory_Controller_Timing_Setu.png

I calculated these values manually by following this "answer record":

http://www.xilinx.com/support/answers/63681.html

By changing the formulas to values in "ps"

CLK Delay  = (<CLK length in ps> + <CLK Package Delay in ps>
DSQ Delay  = (<DQS length in ps> + <DQS Package Delay ps>

DQS to CLK delay = CLK Delay - DQS Delay

DDR_DQS_TO_CLK_DELAY_0 = (341.1058 + 54.536) - (315.2665 + 101.239) = -20.8637 ps ~= -0.021 ns
DDR_DQS_TO_CLK_DELAY_1 = (341.1058 + 54.536) - (317.6282 + 79.5025) =  -1.4889 ps ~= -0.002 ns
DDR_DQS_TO_CLK_DELAY_2 = (249.5747 + 54.536) - (315.6051 + 60.5360) = -72.0304 ps ~= -0.071 ns
DDR_DQS_TO_CLK_DELAY_3 = (249.5747 + 54.536) - (314.9792 + 71.7715) = -82.6400 ps ~= -0.082 ns

The result of manual calculation returns with the calculation of Vivado (2016.01)
with clock 0-1 swapped with 2-3 as it should be.

Still do not return the values preset in the "User Input" that
differentiate significantly from those calculated.

How is it possible ?

Does anyone know how the values were calculated?

If the procedure I used is correct the present default values for MicroZed are
completely wrong but the board works equally ?

I hope someone can clarify this discrepancy, at least be sure of what did I do.

I remain full of doubts.

Thank anyone can help me.

Thanks so much

debugasm

  • 0

    Your observation regarding the mismatch between the CLK 0/1 measurements and CLK 2/3 is correct. We have an error in our board definition files that swapped these measurements. You have correctly listed the accurate measures for these parameters:

    CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {54.14}
    CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {54.14}
    CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {39.7}
    CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {39.7}

    The reason the incorrect values work is due to the way Zynq performs the calibration. With DDR3, the Zynq uses those values as a starting point but then seeks out the most accurate window and uses it's own values determined through calibration.

    In regards to the differences in calculated values between 2016.1 and what Avnet has posted, this is due to differences in the versions of tools used to calculate those values. Xilinx continues to fine-tune how those delays get calculated. The current values were originally calculated with Vivado a few years ago. We saw differences between ISE and Vivado, and then again within different versions of Vivado. Again, for DDR3, it is somewhat irrelevant due to the way Zynq calibrates DDR3. I would consider the most current tools to be the most accurate, but it does not surprise me that multiple sets of values provide a workable interface.

    Thanks for the feedback!

    Bryan

  • 0

    I'm happy to have made a contribution, if all my measurements and observations were incorrect risked permanent madness !!!

    I imagined that the DDR3 Memory Controller however also perform calibration with incorrect values. Then I will use the verified values as the starting values for DDR3 memory controller.

    Thanks very much.

    debugasm