Dear Python developers, dear Alberta/Mario!
We're trying to get a ON Python 1300 module up and running on a microZed board with avnet provided onsemi_python_cam cores and provided bare metal software (from https://github.com/Avnet/hdl).
Reference Design http://zedboard.org/sites/default/files/design/EMBV_PYTHON1300C_HLS_2015_4_02.zip works.
Due to the hardware restrictions in our future product design we would like to run the following configuration, which differs in some central parameters from the reference implementation and onsemi core configuration:
- only 1 instead of 4 LVDS data channels (because we would like to use a cable to transfer the data, therefore a low count of pairs is desired)
- 10bit instead of 8bit pixels
- external LVDS clock instead of external PLL clock (also, because we would like to use a cable)
- just bw image instead of color (not important)
- also we would like to use binning and e.g. SVGA resolution (I think only relevant for bandwidth usage)
Quick calc: 1 LVDS DDR data channel at 135MHz can transfer 27 mega 10b-pixel per second; this results in around 28fps. Good enough.
In the first run we didn't used the onsemi cores at all and designed all ourselves. But we can't get the deserialization stable. Therefore we decided to give the onsemi cores a chance.
Unfortunately this core is hardcoded to use 4 LVDS channels (especially in deserialization section).
I tried to reduce the core (hard coded) to use only one LVDS channel - but to be honest, i haven't fully understood the design architecture (especially deserialization), also my "mother tongue" is Verilog not VHDL. I essence: I'm not aware of the pitfalls while trying this.
Besides the adaption of the onsemi core, another problem is the content of the initialization sequences and configuration registers which of course also have to be altered for 1 LVDS data channel usage (reg 32 and 211?)
Has anybody done something similar to this and can give me some hints. What are the main pitfalls while deserialize the python output? Or rather the adaption of the onsemi core to the above mentioned parameters?
Work done so far (with the onsemi cores):
- changed component.xml to allow 1 LVDS data channel
- altered mainly onsemi_vita_cam_core.vhd to only use 1 LVDS data channel (best effort, don't understand the internals fully)
- setup bare metal SDK, talking to the cores and talking to python works.
- altered register uploads to use 1 LVDS channel
- unfortunately iserdes alignment fails.
Note: with my own implementation of alignment and bitslip I've seen already decoded sync channel bits and incrementing data channel bits on my scope from the python in testpattern mode. But this seems to work only at random, it's not stable. After some powercycle it works, sometimes not...
Any help appreciated. Thanks a lot!
Bye, Marc.
