Microzed XADC pin documentation error?

Question

Hi,

The analog inputs share pins with LVDS inputs. So I wanted a pinout table with both ADC function and digital function. There isn't such a table that I found in the documentation, only separate tables for analog and digital (in the carrier design guide).

So I went a head and made one, and also double checked with the Xilinx package file. They do not match!

To me, it looks like table 5 in the carrier design guide is bad with 9 correct pairs and 7 bad (AD2,3,5,6,10,12,13).

For example, Xilinx puts AD3 together with IO_L9. L9 is called LVDS_8 by Microzed and is mapped to JX2_41,43 But Table five says AD3 is JX2_35,37

Anyone else seen this? Have I missed something?

References:
Carrier design guide: http://zedboard.org/sites/default/files/documentations/MicroZed_Carrier_Design_Guide_rev_1_5.pdf
Xilinx: http://www.xilinx.com/support/packagefiles/z7packages/xc7z020clg400pkg.txt

Former Member · Accepted Answer

Hello Johan,

I think you are being confused by the signal names used on the MicroZed JX connectors. It can happen easily as the board/ PCB signal names, such as JX2_LVDS_6P do NOT follow the same naming convention as the Xilinx Zynq signal names.

JX2_LVDS_6P (which, as you mention above is connected to JX2-35) is in fact connected to the Zynq pin L19, which has a Xilinx signal name of IO_L9P_T1_DQS_AD3P_35. So it is XADC_AD3_P as shown in Table 5.

I believe that the table is correct and you can verify by looking directly at the MicroZed schematic, which is available here:

http://zedboard.org/support/documentation/1519

-Gary