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MicroZed Hardware Design Changing pipeline resolution on Avnet Python1300 IP
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Related

Changing pipeline resolution on Avnet Python1300 IP

Former Member
Former Member over 9 years ago

Hello,

I working with Python 1300 reference design with an HDMI output. I am currently using 1280*1024p resolution but I want to move to 1280*720.
In order to do that, I change settings of my different IP blocs, added axi lite ctrl for potential reprogrammation, change the Pixel frequency to 74.25MHz and the following timing and register in the Onsemi C function:

in: onsemi_vita_sensor_initialize:

         Xuint32 h_active     = 1280;
         Xuint32 h_fporch     = 72
         Xuint32 h_syncwidth  = 80
         Xuint32 h_bporch     = 216
         Xuint32 v_active     = 720;
         Xuint32 v_fporch     = 3
         Xuint32 v_syncwidth  = 5
         Xuint32 v_bporch     = 22

in: vita_spi_seq4:
   { 256, 0xFFFF, 0x9F00}, // //Xst/Xend
   { 257, 0xFFFF, 0x000}, // Ystart
   { 258, 0xFFFF, 0x2CF},//Yend
   { 195, 0xFFFF, 0x01},  //ROI active

So from my understanding:
Register for vita_spi_seq4 control the data transmission of the image from the sensor to the IP setting the right ROI/Resolution. All other communication parameters stay as they were in 1280*1024.
Sync timing change set timing for communication in 1280*720 with the new pixel frequency of 74.25Hz (instead of 108MHz previously).
I put the video timing controller in 720p and I get an output "image" but it is fixed in time and looks like a pink piece of fabric.
Any input on how is the IP working or what I could be missing?
Does the Avnet block support different resolution providing that correct settings have been set into the PS part? Or does it have some IP bug limitation?
Has anyone tested at different rame rate/resolution?

Thanks for your support.
Br,
Ben

Br,
Ben

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  • Former Member
    0 Former Member over 9 years ago

    Hello guys,
    Any ideas of what could the problem be?

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  • Former Member
    0 Former Member over 9 years ago in reply to Former Member

    Hello guys,

    I am working again on this project and I am still struggling to change the resolution of my design which is based on Avnet Python/HDMI reference design.
    Thanks for your support.

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  • Former Member
    0 Former Member over 9 years ago

    benvario,

    I'm not an expert here, but have been working with this hardware on a DMA solution...

    Have you tried leaving the sensor timings at 1280x1024, and only setting the ROI?  From the Python 1300 data sheet, I believe the device is always going to treat the 1280x1024 sensor size as a baseline, and wants us to use ROI for selecting smaller windows. The smaller ROI will result in a 1280x720 data stream that you should be able to convert to HDMI in a downstream IP core.

    Also, the Python PLL clock is actually driven at 27MHz in the reference design. There is a divide-by-4 in the HDL that divides the 108MHz to 27.  You may need to leave that frequency alone as well (otherwise, your 74.25 is divided to 18.56 which doesn't match mult_timer, exposure_time and reset_length registers configured by the initialization code).

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