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MicroZed Hardware Design MIcrozed: The VP/VN pins don't work as advertised
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Related

MIcrozed: The VP/VN pins don't work as advertised

Former Member
Former Member over 10 years ago

As per microzed hardware user guide(v1_5) page-18 the

VP_0_P is mapped to physical pin L10
VN_0_N is mapped to physical pin K9 on ZYNQ

According to the microzed schematic (revF 14018, page 9, U9A)
VP_0_P is connected to K9
VN_0_N is connected to L10 

I would imagine schematic is the correct one, but not sure ?

The PMOD connector also has one connection PMOD_D1 (pin-2 of the diligent connector) is going to K9 of the ZYNQ this matches with the schematic and with the user guide (page - 15, table-11).

I had hooked up an analog signal to the K9 pin and routed to the XADC module's vp, and the vn I have pulled down. The XADC is configured for unipolar mode of operation and hence  vn of the differential pair is grounded. I have also added the following pin constraints
set_property PACKAGE_PIN E9 [get_ports vp_in]
set_property PULLDOWN true  [get_ports vn_in]

And in RTL, I have added the following directives
module top_level(vn_in, vp_in);
(* PACKAGE_PIN = "L10" *) input vn_in;
(* PACKAGE_PIN = "E9" *) input vp_in;


Despite doing all this I am unable to activate the pulldown on the L10; also I am not able get the ADC to sample the vp signal. The exported pin list CSV tells me L10 is not grounded.

One the software side, I am reading the register C_BASEADDRS + 0xc (0x43c0020C) to get the samples. I get a set of consistent readings and those readings are more-or-less similar even when my sensors to ADCs are completely non-functional.

Please do let me know any information that any of you folks have encountered with XADC and dedicated IOs on microzed that would led me on the right path.

Thanks in Advance
-qfpga

CSV
====
IO Bank,Pin Number,IOB Alias,Site Type,Min Trace Delay (ps),Max Trace Delay (ps),Trace Length (um),Prohibit,Interface,Signal Name,Direction,DiffPair Type,DiffPair Signal,IO Standard,Drive (mA),Slew Rate,OUTPUT_IMPEDANCE,PRE_EMPHASIS,LVDS_PRE_EMPHASIS,Pull Type,IN_TERM,DIFF_TERM,OFFCHIP_TERM,Board Signal,Board Voltage
0,L10,IPAD_X0Y1,VN_0,106.858,107.932,,,,vn_in,IN,,,,12,,,,,,,,,,
0,K9,IPAD_X0Y0,VP_0,116.667,117.839,,,,vp_in,IN,,,,12,,,,,,,,,,

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  • Former Member
    0 Former Member over 10 years ago

    You have discovered an error in the MicroZed HW Users Guide. The schematic is correct, package pin L10 is mapped to VN_0_N. Thanks for letting us know about the error.

     

    I am confused about your next statement. Signal PMOD_D1 (pin 2 of the digilent PMOD connector) is connected to Zynq package pin E9, which is shown correctly in both the MicroZed schematic and HW Users Guide, and not K9. E9 is Zynq signal MIO_10. To enable a pull up or pull down on this signal would be done by customizing the Zynq IP block in the Vivado IPI GUI.

     

    -Gary

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  • Former Member
    0 Former Member over 10 years ago

    This post on the Xilinx Community forums might be helpful:

     

    http://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/XADC-Values-not-updating/td-p/571422

     

    -Gary

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