I am using Vivado 2016.2 and am trying to get an AXI Quad SPI device that I have added in PL to work.
So far all I am trying to do is read the registers to ensure that I see the default power-on values. I am reading the control, status, and slave select registers and they all read 0x00000000. I am expecting control=0x180, status=0x0a5, and slave select=0xFFFF. If I write anything to these registers they still read back 0x00000000.
To access these registers I am performing direct memory-mapped reads, with the device base address:
#define XPAR_AXI_QUAD_SPI_0_BASEADDR 0x41E00000
and offsets of 0x60, 0x64, and 0x70 for the three registers.
I have also tried to run the self-test function on it, but it hangs when I do that.
I have configured the IP for standard SPI, with these selections:
Enable XIP Mode - deselected
Enable Performance Mode - deselected
Mode - standard
Transaction Width - 8
Frequency Ratio - 16x1
Enable Master Mode - selected
Enable FIFO - selected
FIFO depth - 16
Enable STARTUP Primitive - deselected
Share the un-used startup ports - deselected
When placing the IP block on the diagram, I connected the ext_spi_clk to s_axi_aclk which is connected to FCLK_CLK0 on the ZYNQ block. This clock is configured for 100 MHz.
Am I missing something in startup or configuration? It seems like this should be pretty simple.
