I use Microzed Xilinx board with Zynq 7010 in a design (with no GTX/GTP/GTH transceivers). The purpose is to use the SATA-IP core in hardware design between AXI interface (from ARM) and SATA port (i.e., differential pins).
Is the following setup possible or it is necessary for the PL side to support GTX/GTP/GTH transceivers for SATA-PHY implementation on Zynq7010?
AXI Bridge (using a code in Reference Design) +
SATA IP core +
SATA PHY (using a code in Reference Design) -->
SATA Differential pins
I would appreciate if anyone can give an advice,