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MicroZed Hardware Design Constraints file for I/O Carrier Card
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Constraints file for I/O Carrier Card

starbright
starbright over 10 years ago

Isn't there a constraints file available for the I/O Carrier card with MicroZed?

I just found this:
Z7010 or Z7020 MicroZed with MBCC-BRK-PCB-A_v2.xdc
but this is for breakout board.

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  • Former Member
    Former Member over 10 years ago +1 verified
    The Master Contraints file has a line for each available signal. To generate a constraints file for your design you will need to either comment out or remove any lines related to pins/signals that you…
  • Former Member
    0 Former Member over 10 years ago

    There is a master constraints file for the MicroZed IO Carrier card on the MicroZed IO Carrier Card Documents page: 

    http://microzed.org/support/documentation/1522

     

    http://microzed.org/sites/default/files/documentations/Z7010%20or%20Z7020%20MicroZed%20with%20MBCC-IO-PCB-D_v2.zip

     

    -Gary

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  • starbright
    0 starbright over 10 years ago

    Thanks. The strange is, that I get almost 100 warnings when using this constraints. Mainly:
    [Common 17-55] 'set_property' expects at least one object.  This are lines like:
    set_property PACKAGE_PIN U14 [get_ports {LED0}];  # "U14.JX1_LVDS_10_P.JX1.41.LED0"

    Is this due to missing lines like:
    set_property IOSTANDARD LVCMOS18 [get_ports {LED0}] ?

    If so - why this is not already included?

    (Sorry for this maybe stupid beginner question)

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  • Former Member
    0 Former Member over 10 years ago

    The Master Contraints file has a line for each available signal. To generate a constraints file for your design you will need to either comment out or remove any lines related to pins/signals that you are not using. In other words, if your design only used two external signals on pins U14 and U15, you would need to comment out or remove all of the "set_property PACKAGE_PIN.." lines EXCEPT for the two below:

    set_property PACKAGE_PIN U14 [get_ports {LED0}];  # "U14.JX1_LVDS_10_P.JX1.41.LED0"
    set_property PACKAGE_PIN U15 [get_ports {LED1}];  # "U15.JX1_LVDS_10_N.JX1.43.LED1"
     
    Then, in your design, you would need to assign those signals the names "LED0" and "LED1" or change the signal names in the "set_property PACKAGE_PIN.." constraint lines to match your signal names.
     
    At the end of the Master Constraints file there are commented example  "set_property IOSTANDARD " constraints for each I/O bank. Un-comment one for each I/O bank that you are actually using and set the appropriate IO standard. As discussed in the comments above these lines make sure they are after any package pin definitions you have in your constraints file.
     
    -Gary
     
     
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  • SpacedCowboy
    0 SpacedCowboy over 10 years ago

    Hi,

    This is a newbie question, but if I have a block design that creates an axi-gpio block, I get an output port that's 31 bits wide. How does one actually assign that to the 8 individual signals ?

    Do you create a module that takes the 31-bit port as an output and 8 1-bit ports (LEDn) as inputs and do a set of assign statements ? Or is there a better way ?

    Cheers
       Simon

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