Logic Speed

Hi,

We know 7010/20 haven't high speed serial transceiver. But event without it, how much speed can we have in LVDS pairs?

And reading parallel data, how much speed can I reach in each pin from FPGA ?

0 zedhed over 11 years ago

Hi robertoalcantara,

If you are familiar with FPGA design then you know that there are a lot of variables which go into a design in order for you to meet timing across all your logic.

However, I believe that the information you are looking for is contained within the Xilinx DS187 document:

http://www.xilinx.com/support/documentation/data_sheets/ds187-XC7Z010-XC7Z020-Data-Sheet.pdf

According to this datasheet, for 7010/7020 -1 speed grade devices, single data rate LVDS transmitter using an OSERDES primitive can achieve up to 600Mbps.

I think your parallel data question is a little more complicated since it seems like it would be dependent upon the I/O standard being used i.e. 3.3V has slower switching than 1.8V I/O.

Regards,

-Kevin
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel