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eFuse Integrity

Former Member

Greetings,

Do the power supply designs for MicroZed and PicoZed meet the requirements described in Xilinx Answer Record #65240?  Here is the link:

Design Advisory for Zynq-7000 AP SoC: Power-On/-Off Sequence Requirements for PS eFUSE Integrity
http://www.xilinx.com/support/answers/65240.html

I think the power supply design handles the power-on sequence very well.  But I'm not sure about the power-off sequence.  MicroZed uses the TLV62130RGT regulator, which has a minimum supply voltage of 3V.  I am concerned that the Power Good (PG) output is not controlled when the input voltage is less than 3V.  The TLV62130RGT regulator also has a floating PG output that complicates analysis.  Please look at the following application report from Texas Instruments regarding the PG output of the TLV62130 and TLV62130A:

http://www.ti.com/lit/an/slva644/slva644.pdf

It says "The TPS62130A device differs from the TPS62130 device only in how the PG (power good) pin is controlled when the device is disabled, in UVLO, or in thermal shutdown. The TPS62130A holds the PG pin low during these conditions, while the TPS62130 sets the PG pin high impedance (floating). This is typically only a concern in a system that uses multiple voltage rails or where an output discharge function is required".

Section 9.3.3 of the TLV62130/A data sheet says "Vin must remain present for the PG pin to stay Low".  I think that implies it needs to be above 3V.

One solution I found is to use a supervisor chip that operates at 0.80V or less.  It needs to monitor both the 1.0V rail as well as VCCO_MIO0 (often 3.3V).  Xilinx has produced a PDF showing one example of a PS_POR_B Supervisor Circuit that ensures the eFuses will not be damaged.  Here is the link:

http://www.xilinx.com/Attachment/AR65240_-_Example_PS_POR_B_Supervisor_Circuit.pdf

In the MicroZed and PicoZed power supplies, how is it guaranteed that the 1.0V rail has not fallen to 0.80V while the 3.3V rail is above 0.9V?  It doesn't look like the 1.0V, 1.8V, and 3.3V voltages are present on the 100-pin connectors, so I don't see a way for the user to monitor them and drive PG_MODULE appropriately.  Vin can be monitored, but Vin could potentially drop before the outputs of the switchers have decayed.  I suppose the user's circuitry could control Vin and the PG_MODULE signal.  I think that would be reliable.  Thank you in advance for evaluating my question.

Regards,

Greg

  • 0

    Hi Greg,

    Unfortunately there is a little interpretation that needs to be done in the Xilinx answer.  Explicitly as it's written, we are fine as it states in the first 3 criteria that both the power on AND power off sequencing are not met to present a problem.  On the next bullet points they say AND / OR.  Originally when this question first came up I was made to believe that as long as the power up sequencing and control signals were held properly then we were not at risk of violating the efuse requirement.  During power up, we meet all these criteria.

    That being said, I did take a capture of the PS_CLK during shutdown and note that it does disable before the 1V supply reaches 0.8V.  During power down the PG signal does begin to float so it is not held low throughout the duration as you pointed out.

    As you mentioned, we do not implement an active shut down scheme to meet these guidelines.  We rely on the decay of each rail to keep us within spec.  These can be measured to show compliance, but do not necessarily guarantee compliance.

    As described by AR# 65240 and based on past discussions, I believe we are meeting the efuse requirements.  Please let me know your thoughts.

    Thanks

    Chris

  • 0

    Hi Chris,

    Thanks for answering my question.  I'm sorry for the delay in replying to your post.  I have been away from work for a couple of days.

    I was concerned about this because the schematics for MicroZed and PicoZed were completed before Xilinx had issued that design advisory, and so the designers of the board wouldn't have know about that problem.

    I agree that the explicit interpretation would lead one to believe it is OK as long as one of either the power-up or power-off criteria is met, but I think that the wording should be "or" in that sentence.  It is good that PS_CLK halts before the 1V supply reaches 0.8V.  That is sufficient to protect the eFuses.  When you performed your test, did you have a significant design loaded in the FPGA?  A large design with lots of clocking will bring down the 1V rail faster, which could present a case where the 1V supply is between 0.4V and 0.8V while the 3.3V supply is above 0.9V (or the 1.8V rail is above 0.7V).

    Thanks,

    Greg