Hello,
With the MicroZed board I pretend to develop some logic, to implement on PL side of Zynq7 020, and I just want to use the PS to generate the clock to PL within the FPGA.
With the ISE 14.5, I instantiated the Processor System and opened it.
With XPS, I defined a clock of 50MHz on FCLK_CLK0, with IO PLL source, and defined it as an external port.
I closed the XPS and on ISE I generated the Top Level of the Processing System.
In the FPGA top level, I connected all u201CProcessing System Top Levelu201D ports to FPGA ports and the clk (FCLK_CLK0) output to my logic (within PL) and also connected the FCLK_CLK0 to a FPGA output.
I generated the bitstream and downloaded the .bit file into the FPGA with success.
After these steps I verified that I do not have a clocking signal at FPGA output. The signal is stuck at High.
Are there some missing steps in my design flow?
Thanks,
