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Change FCLK_CLK1 frequency failed.

Former Member

Hi,

  In my project, Microzed board is used to sample video stream, and format it in FPGA. The internal clock of FPGA is 200MHz, and supplied by FCLK_CLK0. After changing the required frequency to 200MHz in ZYNQ PS7 clock configuration, but the FCLK_CLK0 is still 100MHz. Also I checked the register value of OxF8000180 in PS7_init.c, it is OK as below:
    // .. .. SRCSEL = 0x0
    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
    // .. .. DIVISOR0 = 0x5
    // .. .. ==> 0XF8000180[13:8] = 0x00000005U
    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
    // .. .. DIVISOR1 = 0x1
    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
    // .. ..
    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100500U).

Anyone can help me?


  • 0

    Hello Hunter,

     

    Did your modified PS7_init.c actually execute by either starting a 'Run' or 'Debug' session in the SDK with the PS7_init.c checked or by booting with an FSBL that has your FCLK_CLK0 programming implemented? The FCLK_CLK0 will not be active until you do one or the other.

     

    I have not looked closely at your code snippet but I was able to go double-click on the Zynq IP block in Vivado and, under 'Clock Configuration' > PL Fabric Clocks, modify the FCLK_CLK0 frequency and see the change with the clock signal routed out to a PL pin for observation.

     

    -Gary