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MicroZed Microheader Configuration

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Hi Guys,

Apologies for asking a stupid question but I have tried searching everywhere and cannot find an answer.

I want to control the PL GPIO from Xilinx SDK. All tutorials show how to do similar using PS MIO which is nice and easy. I can't work out how to configure the hardware design so that I can access JX1 and JX2 microheaders. My understanding leads me to believe that I will need an AXI_GPIO block, but I am unsure of how to configure it such that it points to JX1 or JX2.

Thanks in advance for any help,

Stephen

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    I think I worked it out through perseverance. Posting my (hopeful) basic solution for if anyone else stumbles across this stuck. Please correct me if I am wrong.


    Ok. The microheaders, JX1 and JX2 are I/O connected to the PROGRAMMABLE LOGIC. In a Zynq, to control programmable logic I/O with the processing system, you need an AXI interface, and an AXI GPIO module. That GPIO module must then have a port connected to it, and that port must be mapped (in the VIVADO PROJECT CONSTRAINTS) to the actual physical pin on JX1 or JX2. 'http://imgur.com/0ap9eQx' shows what the Vivado hardware block diagram must look like, to enable the use of a SINGLE port on JX1. The constraints file must contain the following HDL:

    set_property PACKAGE_PIN R19 [get_ports {GPIO_Out}];
    set_property IOSTANDARD LVCMOS18 [get_ports -filter { IOBANK == 34 }]

    IOBANK == 34 is because JX1 is connected to Bank 34. Pin R19 was arbitrarily chosen. GPIO_Out is the name of the port in the Vivado HW schematic. IOSTANDARD LVCMOS18 means the VccIO will be 1.8V, so the VccIO jumper on the breakout board must be placed to reflect this.

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