Hello
I want to develop a carrier board for my MicroZed Zynq 7020 RefF07.
I checked the MicroZed documents.
I found that Bank 34 and Bank 35 are routed in differential topology. (in each Bank there are two single ended traces, named SE pins)
in Bank 34 there is a pin named PUDC_B.
now my question:
if I don't use XADC and ... can I use all Bank 34/35 pins as regular I/O?
bcoz my high speed ADC has 15 LVDS pairs (totally 30 pins) and I want to dedicate Bank 34 to the ADC.
also the ADC has one LVDS output clock. I want to connect it to MRCC pins in the Bank 34.
What does it mean C section?
http://s8.picofile.com/file/8313213000/micozed_pins.PNG
Best Regards
