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GPIO Signal Reflection, is this normal?

Former Member

Hi,

I'm using the GPIO on the MIO 500 PMOD to interface a SPI controller for an image sensor, with SCK running 5MHz. A logic level translator is used (3.3V -> 2.0V) in between but signal coming out from translator is very bad. I probed the input and saw signal ringing/reflection on transition edges. At first I suspect it was due to the dupont wire I'm using so I decided to probe a clean microZED directly on the PMOD soldering pin.

But I still observe the same effect.

https://dl.dropboxusercontent.com/u/83845564/20150921_144957.jpg

May I ask if this is the intended behavior from design or I have to do something to alleviate it?

  • 0

    Hi there,

    The screen capture was very helpful.  I honestly do not think the ringing is your issue.

    Remember that depending on the TYPE of logic level your translator uses, being too high is not an issue.  This is with the understanding that you are not exceeding the voltage tolerance of the part nor saturating a NON-Rail to rail part.  Nor is the RING an issue if the ring is not dropping below the logic "off" level of the input logic type of the receiving part.

    It sounds like you are still experimenting.  The nice part about the FPGA fabric driving that line, you can tune the drive strength.  In the XDC file you can set the drive current to low output, which should help you.  You can also mess with the slew value.  The fastest way to do this is edit the XDC file.  The easiest way is right in the I/O Manager in Vivado.  To get to the I/O Manager, run the Design through the project flow until you can open the implemented design.  Then under the LAYOUT pull-down menu, you will see I/O Planning.  From there, you can choose the drive strength and Slew Type, as well as IO Standard among the many options.

    For help on writing constraints, you can see UG903.
    Here is good definition of slew rate, which might help you understand what to try:

    This comes from an older UCF based document (UG625).

    The Slew (SLEW) constraint:
    u2022 Defines the slew rate (rate of transition) behavior of each individual output to the
    device.
    u2022 May be placed on any output or bi-directional port to specify the port slew rate to be:
    u2013 SLOW (default)
    u2013 FAST
    u2013 QUIETIO (Spartanu00AE-3A devices only)
    Use the slowest Slew attribute available to the device while still allowing applicable I/O
    timing to be met in order to minimize any possible signal integrity issues.

    I've personally used SLOW slew for signals over 50Mhz without issue.  You should be fine using 5MHz.

    --Dan

  • 0 in reply to drozwood90

    Hi Dan,

    Yes, I kind of agree that input overshoot/undershoot might not be the issue that directly relates to the logic translator output. I'm going to double check the probe compensation and GND lead. The slew rate on the MIO is also set to be "Slow" with "pull up" disabled.

    The following is the output.
    https://dl.dropboxusercontent.com/u/83845564/20150917_214544.jpg

    Looks like some very weird stray capacitance charge/discharge during transitions. I really could not find out why. I'll update when I have more information.

    Thanks for the advice on IO configuration.

  • 0

    I agree about the capacitance.  I would have said you had the probes set to AC coupled.  It looks like in the screen capture it is set to DC?  Can you confirm this?

    If you can, might I suggest slowing the signal down just to see what it looks like?  What MicroZed / carrier card are you using?  What PMOD pin did you attach to?  I'd like to help track this down if possible.

    --Dan

  • 0 in reply to drozwood90

    Yes the probe was DC coupled so I could verified the actual min/max voltage.
    I'm not using carrier card and all the signals were connected using jumper cable from J5 PMOD connector. The 3.3V from microzed is only used to drive a voltage translator FLXA108 chip, nothing else.

    I would really appreciate your help. I'm struggling to figure out what's causing this instability issue here. Since I do not own a scope, I only have access occasionally from a lab on my university.

  • 0

    What does the output of your translator look like?  From what you linked in the images, I do not see an issue.

  • 0

    Hi there,

    It seems the issue is in your translator.  If not notice, there is a lot of missed clock edges.  From what I read in the datasheet of the part, IF You have 3.0V on A and 2.0V on B it is rated ABOUT 100Mhz.

    At this point, I do not see an issue with the FPGA.  It seems the translator is not working.

    Have you checked that you are controlling the flow signals properly (there are enable pins).
    You could setup some code tied to a button.  When you press the button, put a single pulse to the translator and capture the output.  See if that functions.

    Is there a reason you do not just run the bank voltage at 2.0V?  You could eliminate the translator by doing that.  What is on the other side of the translator?  Does that have a high capacitance?

    --Dan

  • 0 in reply to drozwood90

    Hi,

    I forgot to mention the yellow trace is the SCK and the Green trace is the MOSI. Thus there's no missing edges on green signal except both are struggling to be pulled to high or low. The OE is tied to the GND on layout and schematics.

    I have to run the SPI controller from MIO 3.3V because both PL banks are used up for LVDS receiver, a total of 32 pairs of signal from the image sensor. The VCCIO_34 and 35 have to be set at 2.5V in order to achieve 100ohm internal termination. In any case, should the EMIO be used for SPI controller, a 2.5V -> 2V translator is also required.

    I measure the signal with open circuit on the socket without any load. Thus it should not be a problem. I'm going to check the soldering joints.

  • 0

    Jack,

    That helped me to properly understand the images.  Thank you. 

    I now go back to one of my original questions.  What is the logic TYPE you are using on the receiving end of the 2.0V?  I am not really seeing an issue here.  The fact that is has a "capacitive" effect likely means nothing if the logic level is LVCMOS.

    --Dan