Hi everyone, (any one please!)
I'm not great with processor architectures and software development.
I've been trying to get a simple application running where an HDL module controls the state of the user LED.
I can do this on the processor side, but I haven't been able to have the processor check the state of my HDL port.
I know there are a number of ways to do this, like sharing dual port RAM, I would like to implement the most direct method, which I think is using the EMIO directly.
Please correct my understanding of this:
When I enable the EMIO in the Zynq7 Processing System a port is created called GPIO_0. I specified the width as 1, and connected it to my HDL modules port in the wrapper.
So in the application, I should be able to check the state of MIO 54, the first EMIO pin. However when I do this the value is 0, which isn't correct.
Okay, so do I need to connect the AXI interconnect for this? How would this be done to have the PS check the state of a PL port? Do I need to instantiate the AXI in the wrapper as well as in the block design?
Any guidance is much appreciated, I've been at this for a while now trying to get my head around the AXI
Thanks
Sam
