We've been adapting the Avnet Python 1300C HDMI / framebuffer reference design into a pure DMA design (no HDMI) and have run into a couple of questions -
- The Avnet design drives the Python PLL clock at 27MHz, much slower than the 72MHz called for in the Python data sheet. This significantly limits the frame rate as the PLL clock governs the per-frame readout time. The data sheet says 72MHz is required to achieve its rated frame rates (165fps @ 1280x1024), and doing the math on the frame reset_length bears this out.
Are there any reference designs that drive the Python PLL clock at 72MHz?
- When we set a ROI sub-window via Python registers, we're seeing frames partially corrupted. The corruption only happens when we set X bounds to something other than [0,1279]. (Y bounds work fine.) The corruption gets worse the smaller the total width. Below are two examples of a corrupted test pattern:
Any ideas what might be causing this? I have combed through the data sheet and tried many settings but nothing changes it.