Microzed 7020 Device Tree

Hello,

I have a 7020 Microzed. I am currently building the image with Yocto with the Gen-Machine-Conf Parse-SDT workflow from AMD. 

I am attempting to get the USB PHY to work. I would like to to be in peripherial mode, but I can't get it working at all. 

Gen-Machine-conf gives me the standard device tree files, and I am using a custom DTSI that is included in the system-top.

Does anyone know what I'm doing wrong?

/dts-v1/;
#include "zynq-7000.dtsi"
#include "pl.dtsi"
#include "pcw.dtsi"
/ {
	device_id = "7z020";
	slrcount = <1>;
	family = "Zynq";
	speed_grade = "1";
	VIPER_FPGA_PIXBUF_memory: memory@40000000 {
		compatible = "xlnx,axi-bram-ctrl-4.1";
		xlnx,ip-name = "axi_bram_ctrl";
		device_type = "memory";
		memory_type = "memory";
		reg = <0x40000000 0x200000>;
	};
	VIPER_FPGA_REGS_memory: memory@80000000 {
		compatible = "xlnx,axi-bram-ctrl-4.1";
		xlnx,ip-name = "axi_bram_ctrl";
		device_type = "memory";
		memory_type = "memory";
		reg = <0x80000000 0x80000>;
	};
	ps7_qspi_linear_0_memory: memory@fc000000 {
		compatible = "xlnx,ps7-qspi-linear-1.00.a-memory";
		xlnx,ip-name = "ps7_qspi_linear";
		device_type = "memory";
		memory_type = "linear_flash";
		reg = <0xfc000000 0x1000000>;
	};
	ps7_ddr_0_memory: memory@00100000 {
		compatible = "xlnx,ps7-ddr-1.00.a";
		xlnx,ip-name = "ps7_ddr";
		device_type = "memory";
		memory_type = "memory";
		reg = <0x00100000 0x3FF00000>;
	};
	ps7_ram_0_memory: memory@0 {
		compatible = "xlnx,ps7-ram-1.00.a";
		xlnx,ip-name = "ps7_ram";
		device_type = "memory";
		memory_type = "memory";
		reg = <0x0 0x30000>;
	};
	ps7_ram_1_memory: memory@ffff0000 {
		compatible = "xlnx,ps7-ram-1.00.a";
		xlnx,ip-name = "ps7_ram";
		device_type = "memory";
		memory_type = "memory";
		reg = <0xffff0000 0xfe00>;
	};
	chosen {
		stdout-path = "serial0:115200n8";
	};
	aliases {
		serial0 = &uart1;
		spi0 = &qspi;
		serial1 = &coresight;
		spi1 = &VIPER_TRIGDAC_SPI;
		spi2 = &VIPER_ADC_SPI;
		ethernet0 = &gem0;
	};
	cpus_a9: cpus-a9@0 {
		compatible = "cpus,cluster";
		address-map = <0xf0000000 &amba 0xf0000000 0x10000000>, 
			      <0x40000000 &VIPER_FPGA_PIXBUF_memory 0x40000000 0x200000>, 
			      <0x40000000 &VIPER_FPGA_PIXBUF 0x40000000 0x200000>, 
			      <0x80000000 &VIPER_FPGA_REGS_memory 0x80000000 0x80000>, 
			      <0x80000000 &VIPER_FPGA_REGS 0x80000000 0x80000>, 
			      <0x00100000 &ps7_ddr_0_memory 0x00100000 0x3FF00000>, 
			      <0x0 &ps7_ram_0_memory 0x0 0x30000>, 
			      <0xffff0000 &ps7_ram_1_memory 0xffff0000 0xfe00>, 
			      <0x40200000 &axi_gpio_0 0x40200000 0x10000>, 
			      <0x81e00000 &VIPER_ADC_SPI 0x81e00000 0x10000>, 
			      <0x81e10000 &VIPER_TRIGDAC_SPI 0x81e10000 0x10000>, 
			      <0x83c00000 &axi_xadc_0 0x83c00000 0x10000>, 
			      <0xf8008000 &ps7_afi_0 0xf8008000 0x1000>, 
			      <0xf8009000 &ps7_afi_1 0xf8009000 0x1000>, 
			      <0xf800a000 &ps7_afi_2 0xf800a000 0x1000>, 
			      <0xf800b000 &ps7_afi_3 0xf800b000 0x1000>, 
			      <0xf8800000 &coresight 0xf8800000 0x100000>, 
			      <0xf8006000 &mc 0xf8006000 0x1000>, 
			      <0xf8007000 &devcfg 0xf8007000 0x100>, 
			      <0xf8004000 &ps7_dma_ns 0xf8004000 0x1000>, 
			      <0xf8003000 &dmac_s 0xf8003000 0x1000>, 
			      <0xe000b000 &gem0 0xe000b000 0x1000>, 
			      <0xf8f00200 &global_timer 0xf8f00200 0x100>, 
			      <0xe000a000 &gpio0 0xe000a000 0x1000>, 
			      <0xf8900000 &ps7_gpv_0 0xf8900000 0x100000>, 
			      <0xf8f01000 &intc 0xf8f01000 0x1000>, 
			      <0xe0200000 &ps7_iop_bus_config_0 0xe0200000 0x1000>, 
			      <0xf8f02000 &L2 0xf8f02000 0x1000>, 
			      <0xf800c000 &ps7_ocmc_0 0xf800c000 0x1000>, 
			      <0xf8891000 &ps7_pmu_0 0xf8891000 0x1000>, 
			      <0xe000d000 &qspi 0xe000d000 0x1000>, 
			      <0xfc000000 &ps7_qspi_linear_0_memory 0xfc000000 0x1000000>, 
			      <0xf8f00000 &ps7_scuc_0 0xf8f00000 0xfd>, 
			      <0xf8f00600 &scutimer 0xf8f00600 0x20>, 
			      <0xf8f00620 &scuwdt 0xf8f00620 0xe0>, 
			      <0xe0100000 &sdhci0 0xe0100000 0x1000>, 
			      <0xf8000000 &slcr 0xf8000000 0x1000>, 
			      <0xe0001000 &uart1 0xe0001000 0x1000>, 
			      <0xe0002000 &usb0 0xe0002000 0x1000>, 
			      <0xf8007100 &adc 0xf8007100 0x21>;
		#ranges-address-cells = <0x1>;
		#ranges-size-cells = <0x1>;
	};
};
#include "VM_Latest_V24p2_NHW.dtsi"

Thanks in advance!

// SPDX-License-Identifier: GPL-2.0
/*
 * USB peripheral fix for Avnet MicroZed (Zynq-7000)
 * Keeps baseline bootability while correcting ULPI PHY definition.
 */

 /include/ "zynq-7000.dtsi"

/ {
	model = "Avnet MicroZed board";
	compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";

	amba: amba {
		usb0: usb@e0002000 {
			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
			reg = <0xe0002000 0x1000>;
			interrupt-parent = <&intc>;
			interrupts = <0 21 4>;
			clocks = <&clkc 28>;
			dr_mode = "peripheral";
			usb-phy = <&usb_phy0>;
			status = "okay";
		};

		usb_phy0: phy0 {
			compatible = "ulpi-phy";
			#phy-cells = <0>;
			view-port = <0x170>;
			drv-vbus;
		};
	};

	aliases {
		ethernet0 = &gem0;
		serial0 = &uart1;
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x40000000>;
	};

	chosen {
		bootargs = "earlycon";
		stdout-path = "serial0:115200n8";
	};
};

&clkc {
	ps-clk-frequency = <33333333>;
};

&gem0 {
	status = "okay";
	phy-mode = "rgmii-id";
	phy-handle = <&ethernet_phy>;

	ethernet_phy: ethernet-phy@0 {
		reg = <0>;
	};
};

&sdhci0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};