PCIe hw design

I have opened the mini ITX PCIe design in Vivado, and can not find how the interrupt is connected, it is made external in block design

and left UNCONNECTED in toplevel?

.pcie_interrupt_out(pcie_interrupt_out)

does the PCIe core not use interrupts at all?

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0 Former Member over 11 years ago

doenst matter, in our design we had it connected properly and it works:

00:00.0 Non-VGA unclassified device: Xilinx Corporation Device 0782
01:00.0 SATA controller: Device 1c28:0122 (rev 14)
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0 Former Member over 11 years ago

doenst matter, in our design we had it connected properly and it works:

00:00.0 Non-VGA unclassified device: Xilinx Corporation Device 0782
01:00.0 SATA controller: Device 1c28:0122 (rev 14)
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Vote Up 0 Vote Down

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