I was reviewing the mini-itx schematic, Rev D., and had a question about U40 (DSC557-0343FI0), which provides the PCIe reference clock to the PCIe connector and the zynq. I noticed that the reference design connects CLK0+ on the chip to CLK0_N and CLK0- to CLK0_P and similarly for CLK1. Is there a particular reason that the positive is connected to the negative?
I suspect is doesn't matter as long as the same phase clock is provided to both the zynq and the PCIe connector. We are laying out a custom board and just wanted to check on this before we have the board fabricated.
Regards.
