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Mini-ITX Hardware Design PS freezes when making use of PL
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PS freezes when making use of PL

cone83
cone83 over 9 years ago

I am encountering very odd problems with my new Mini-ITX board. Whenever I make use of a significant portion of the PL resources, the PS just freezes.

I have done quite a lot of debugging on this, and the only thing that seems to affect this problem is the amount of resources used. I have a test design that does a lot of useless computations. If I allow Vivado to optimize away all the useless stuff and hence greatly reduce the resource usage, then the CPU does not freeze. If I prevent the optimization and use 56% LUTs, then the CPU freezes immediately.

There are no timing timing violations or other errors reported by Vivado. I have now come to a point where I suspect that my Zynq might actually be damaged.

I have created a set of boot files for reproducing this error on a Mini-ITX with Zynq 7100. The boot files can be downloaded here:
https://mega.nz/#F!9hF0kQrZ!RfGgoTnCO0QOtp6MSUFZxg

When booting this configuration, U-boot only manages to print a few lines on UART before the CPU stalls. Usually the output looks like this:

--------------
U-Boot 2015.07-dirty (Apr 09 2016 - 11:32:21 +0200)

Model: Zynq Mini-ITX Board
DRAM:  ECC disabled 1 GiB
MMC:   zynq_sdhci: 0
SF: Detected S25FL128S_64K with page size
--------------

Sometimes it even freezes before being able to print the first line. I would be really thankful if somebody could try out those boot files and report if this error also occurs on other Mini-ITX boards with Zynq 7100 SoCs.

Many thanks

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  • Former Member
    0 Former Member over 9 years ago

    Hello,

     

    You mention in the post above that you are using Vivado 2015.4.1 on Linux. I have seen an issue in the past where Vivado on Linux created incorrect frequencies for PL fabric clocks if the regional settings for the Linux were set to something other than 'US'. Here is a post to the Xilinx Community forums and one on this forum that relate to that issue:

     

    https://forums.xilinx.com/t5/Embedded-Development-Tools/Cannot-Set-specific-clock-frequency-for-PL-Fabric-Clocks-in/td-p/528867/page/2

     

    http://zedboard.org/content/ethernet-does-not-work-linux-314

     

    I don't know if this is an issue in the current version of Vivado, but it might be worth changing the Linux regional setting and regenerating your application to rule it out.

     

    -Gary

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  • Former Member
    0 Former Member over 9 years ago

    Hello,

     

    You mention in the post above that you are using Vivado 2015.4.1 on Linux. I have seen an issue in the past where Vivado on Linux created incorrect frequencies for PL fabric clocks if the regional settings for the Linux were set to something other than 'US'. Here is a post to the Xilinx Community forums and one on this forum that relate to that issue:

     

    https://forums.xilinx.com/t5/Embedded-Development-Tools/Cannot-Set-specific-clock-frequency-for-PL-Fabric-Clocks-in/td-p/528867/page/2

     

    http://zedboard.org/content/ethernet-does-not-work-linux-314

     

    I don't know if this is an issue in the current version of Vivado, but it might be worth changing the Linux regional setting and regenerating your application to rule it out.

     

    -Gary

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  • cone83
    0 cone83 over 9 years ago in reply to Former Member

    Hi Gary,

    I really appreciate your help on this. I'm aware of Vivado's problems with coping with different regional settings. That's why I already switched all settings to English on my system. I also just tried downgrading to 2015.2 and it produced the same result.

    I think that the same error might also be responsible for my problems with getting PCIe running (other thread), as the PCIe data is also passed through a HP_AXI port. I have ordered the same NIC that is used in the reference design, but that is another topic.

    I'll try if I can get a Windows machine to do a test-build, but building on Windows wouldn't be a longterm solution.

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