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Mini-ITX Hardware Design Not seeing PCIe with custom project
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Related

Not seeing PCIe with custom project

Former Member
Former Member over 10 years ago

Hello!

I have a 7z100 miniITX board, and I have been able to run through the entirety of the wonderful "Ubuntu Desktop Linux" instructions, and got Ubuntu 12.11 running. I was then able to get Ubuntu 14.04 running from the Linaro 14.10 developer build. I believe I have everything running... except for PCIe.

I have been trying a number of things (modifications to my device tree, different kernel configuration options, using the "linux-xlnx" Xilinx kernel instead of the Analog Devices kernel the "Ubuntu Desktop Linux" instructions use, etc), but nothing has worked yet.

I've verified that the board itself is okay by taking the ready_to_testsd_image_nic file from the "PCIe Root Complex Reference Design" project. I can see the PCIe bus, and I can see a card identified if one is plugged in, at boot and using lspci.

I've changed my .bit/.hdf files to the ones used in the "PCIe Root Complex Reference Design", and I've rebuilt the FSBL, and BOOT.bin. I have used menuconfig on the linux-xlnx kernel to ensure the PCIe support is built-in, and I've tried several different changes to the device tree's pci bus, comparing what building a device tree using these instructions: http://www.wiki.xilinx.com/Build+Device+Tree+Blob
generates versus what is listed in the .patch file from the "PCIe Root Complex Reference Design" project. I had to make changes to the generated ethernet device in the device tree to get it to function, so that made me suspicious that the generated device tree was incomplete/incorrect.

For comparison, here is what dmesg and lspci have to say about available devices on my Ubuntu 14.04 build:

root@linaro-developer:~# dmesg | grep pci
ehci-pci: EHCI PCI platform driver
root@linaro-developer:~# lspci -vvv

and here is what the example project reports to the same commands:

zynq> dmesg | grep pci
xaxi_pcie_set_bridge_resource:pci_space: 0x02000000 pci_addr:0x0000000060000000 size: 0x0000000010000000
xaxi_pcie_set_bridge_resource:Setting resource in Memory Space
PCI host bridge /amba@0/axi-pcie@50000000 (primary) ranges:
pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
pci_bus 0000:00: root bus resource [io  0x1000-0xffff]
pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
pci 0000:00:00.0: [10ee:0706] type 01 class 0x060400
pci 0000:00:00.0: reg 10: [mem 0x00000000-0x3fffffff]
pci 0000:01:00.0: [10de:1183] type 00 class 0x030000
pci 0000:01:00.0: reg 10: [mem 0x00000000-0x00ffffff]
pci 0000:01:00.0: reg 14: [mem 0x00000000-0x07ffffff 64bit pref]
pci 0000:01:00.0: reg 1c: [mem 0x00000000-0x01ffffff 64bit pref]
pci 0000:01:00.0: reg 24: [io  0x0000-0x007f]
pci 0000:01:00.0: reg 30: [mem 0x00000000-0x0007ffff pref]
pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 01
pci 0000:00:00.0: BAR 0: can't assign mem (size 0x40000000)
pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x6bffffff]
pci 0000:00:00.0: BAR 7: assigned [io  0x1000-0x1fff]
pci 0000:01:00.0: BAR 1: assigned [mem 0x60000000-0x67ffffff 64bit pref]
pci 0000:01:00.0: BAR 3: assigned [mem 0x68000000-0x69ffffff 64bit pref]
pci 0000:01:00.0: BAR 0: assigned [mem 0x6a000000-0x6affffff]
pci 0000:01:00.0: BAR 6: assigned [mem 0x6b000000-0x6b07ffff pref]
pci 0000:01:00.0: BAR 5: assigned [io  0x1000-0x107f]
pci 0000:00:00.0: PCI bridge to [bus 01]
pci 0000:00:00.0:   bridge window [io  0x1000-0x1fff]
pci 0000:00:00.0:   bridge window [mem 0x60000000-0x6bffffff]
ehci-pci: EHCI PCI platform driver
zynq> lspci
00:00.0 Class 0604: 10ee:0706
01:00.0 Class 0300: 10de:1183
zynq>

Does anyone have any places for me to start looking? At this point, I'm happy to share device tree files, .config files, or try anything anyone suggests.

I do have one direct question: One difference between the "PCIe Root Complex Reference Design" kernel and the latest from the linux-xlnx master is the version: the example project uses 3.9 while the latest is 3.18. One Xilinx-PCIe-related change in 3.18 is the axi-pcie driver has been mainlined for the first time. Could it be there is a problem with the kernel build that the new mainlined driver isn't being included?

Any help or suggestions are greatly appreciated, in the mean time I will attempt to get an older kernel built and see if that makes a difference, and report back! Thanks!

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  • Former Member
    0 Former Member over 10 years ago

    I agree that the issues are now isolated to the device tree and/or kernel configuration.  Check this link for some additional optional parameters for kernel configuration on Zynq for PCIe.  

    http://www.wiki.xilinx.com/Linux+PCIe

    Hopefully that will provide the clues to all you to correct any omissions in your kernel configuration.  If it appears the configuration settings you are using is complete, then the problem must be in the device tree, so you need to verify that the address map of your design corresponds precisely to the one specified in your device tree.  Pay close attention to the interrupt settings, which appear to have changed between releases.

    Ron

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  • Former Member
    0 Former Member over 10 years ago

    I agree that the issues are now isolated to the device tree and/or kernel configuration.  Check this link for some additional optional parameters for kernel configuration on Zynq for PCIe.  

    http://www.wiki.xilinx.com/Linux+PCIe

    Hopefully that will provide the clues to all you to correct any omissions in your kernel configuration.  If it appears the configuration settings you are using is complete, then the problem must be in the device tree, so you need to verify that the address map of your design corresponds precisely to the one specified in your device tree.  Pay close attention to the interrupt settings, which appear to have changed between releases.

    Ron

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