Hi All,
I question the use of the PS_FCLK_0 (125 Mhz) output clock in the reference design. Why not use the AXI_PCI_ACLK directly instead? This will eliminate the need for clock-domain crossing couplers in the axi_interconnect, improving the latency and utilization of the interconnect. Additional logic could be saved by using a second MP_AXI_GP1 PS port for the PCIE S_AXI_CTRL (32-bit) interface.
Am I missing something?
