Hello everyone,
I need to work with the Mini-ITX board. But as this is unfortunately the first board Iu2019m really working with, there are a lot of barriers for me. Such as general terms, the vivado software, the creation of testbenches etcu2026 So my problem described here is more of a general nature, than board specific I guess.
I need a single ended clock signal within my VHDL code. So in terms of using the internal 200MHz clock (LVDS) I got through many documentation and finally instantiating the IBUFGDS exactly as it is stated in the Xilinx document (7series_hdl.pdf u2013 page 177/446)- see below. I connect the inputs (I & IB) to the following pins as stated in the constraints file (.xdc):
## 200MHz System Clock
set_property PACKAGE_PIN H9 [get_ports CLK_P]
set_property PACKAGE_PIN G9 [get_ports CLK_N]
set_property IOSTANDARD LVDS [get_ports CLK_P]
set_property IOSTANDARD LVDS [get_ports CLK_N]
In my top entity I have the inputs CLK_N & CLK_P as std_logic and in the u201Carchitecture Behavioral of u2026u201D I put the above named IBUFGDS like this:
-- IBUFGDS: Differential Global Clock Input Buffer
-- 7 Series
-- Xilinx HDL Libraries Guide, version 14.7
IBUFGDS_inst : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => clk, -- Clock buffer output
I => CLK_P, -- Diff_p clock buffer input (connect directly to top-level port)
IB => CLK_N -- Diff_n clock buffer input (connect directly to top-level port)
);
-- End of IBUFGDS_inst instantiation
May I now use the signal u201Cclku201D for further parts in the code? As a friend stated to me the buffer is physically attached as an analog circuit (e.g. like some pull-up resistors) to the pin of the FPGA and is thereby something like an output. Thatu2019s why I would need to connect it externally by a short the get it as an input again (of cause using an input buffer again).
To my mind it should be possible to set up the internal clock, although it is LVDS like, and use it directly internally, without any external detour. When I checked the IPs includable e.g. for an block design it should also be possible to get several clock frequencies just as one needs them.
The overall goal is to create a clock signal used for a 9600baud UART interface. A clock divider is used in the further code.
In case this information is needed: Iu2019m working on a windows 7 host system, with Vivado 2015.4.
Any help for my problem is welcome. Thanks in advance.
