Hi All,
For a project I am trying to get the Zynq_mini_itx up and running with USB ports. Used the zynq_mini_itx_board_filesv2015_3.zip and followed the manual.
I managed to get a working image however the USB ports are not showing up. Read on the internet that in some cases you need to update the device tree form OTG to host. However this did not resolve my issue. Since I want to connect a VCOM with CDC_ACM module. Previously on 2015.2 this was working for me but for other reasons we switched to 2015.4 (vivavo and petalinux)
Below you find my dmesg output:
Booting Linux on physical CPU 0x0
Linux version 4.0.0-xilinx (x@localhost.localdomain) (gcc version 4.9.2 (Sourcery CodeBench Lite 2015.05-17) ) #2 SMP PREEMPT Tue Mar 8 09:23:12 CET 2016
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine model: Mini-ITX-Zedboard-UWBRx-v2
bootconsole [earlycon0] enabled
cma: Reserved 16 MiB at 0x3f000000
Memory policy: Data cache writealloc
On node 0 totalpages: 262144
free_area_init_node: node 0, pgdat c0b7b300, node_mem_map eeff7000
Normal zone: 1520 pages used for memmap
Normal zone: 0 pages reserved
Normal zone: 194560 pages, LIFO batch:31
HighMem zone: 67584 pages, LIFO batch:15
PERCPU: Embedded 11 pages/cpu @eefd3000 s12672 r8192 d24192 u45056
pcpu-alloc: s12672 r8192 d24192 u45056 alloc=11*4096
pcpu-alloc: [0] 0 [0] 1
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260624
Kernel command line: console=ttyPS0,115200 earlyprintk
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1011060K/1048576K available (4779K kernel code, 224K rwdata, 1716K rodata, 5004K init, 208K bss, 21132K reserved, 16384K cma-reserved, 253952K highmem)
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
vmalloc : 0xf0000000 - 0xff000000 ( 240 MB)
lowmem : 0xc0000000 - 0xef800000 ( 760 MB)
pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
.text : 0xc0008000 - 0xc066013c (6497 kB)
.init : 0xc0661000 - 0xc0b44000 (5004 kB)
.data : 0xc0b44000 - 0xc0b7c060 ( 225 kB)
.bss : 0xc0b7c060 - 0xc0bb03f4 ( 209 kB)
Preemptible hierarchical RCU implementation.
Additional per-CPU info printed with stalls.
RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS:16 nr_irqs:16 16
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
slcr mapped to f0006000
zynq_clock_init: clkc starts at f0006100
Zynq clock init
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 3298534883328ns
timer #0 at f000a000, irq=17
Console: colour dummy device 80x30
Calibrating delay loop... 1332.01 BogoMIPS (lpj=6660096)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x486310 - 0x486368
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (2664.03 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
cpuidle: using governor ladder
cpuidle: using governor menu
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0xf0080000
GPIO IRQ not connected
XGpio: /amba_pl/gpio@81200000: registered, base is 898
GPIO IRQ not connected
XGpio: /amba_pl/gpio@81210000: registered, base is 890
GPIO IRQ not connected
XGpio: /amba_pl/gpio@81220000: registered, base is 887
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
media: Linux media interface: v0.10
Linux video capture interface: v2.00
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
Advanced Linux Sound Architecture Driver Initialized.
Switched to clocksource arm_global_timer
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP: reno registered
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
PCI: CLS 0 bytes, default 64
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
futex hash table entries: 512 (order: 3, 32768 bytes)
jffs2: version 2.2. (NAND) (SUMMARY) u00A9 2001-2006 Red Hat, Inc.
bounce: pool size: 64 pages
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dmac: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 144, base_baud = 3125000) is a xuartps
console [ttyPS0] enabled
bootconsole [earlycon0] disabled
xdevcfg f8007000.devcfg: ioremap 0xf8007000 to f007e000
[drm] Initialized drm 1.1.0 20060810
brd: module loaded
loop: module loaded
tun: Universal TUN/TAP device driver, 1.6
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
CAN device driver interface
libphy: MACB_mii_bus: probed
macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 146 (00:0a:35:00:1e:53)
macb e000b000.ethernet eth0: attached PHY driver [Marvell 88E1510] (mii_bus:phy_addr=e000b000.etherne:00, irq=-1)
e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
usbcore: registered new interface driver cdc_acm
cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
cdns-i2c e0004000.i2c: 400 kHz mmio e0004000 irq 141
Xilinx Zynq CpuIdle Driver started
Driver 'mmcblk' needs updating - please use bus_type methods
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
sdhci-arasan e0100000.sdhci: No vmmc regulator found
sdhci-arasan e0100000.sdhci: No vqmmc regulator found
mmc0: SDHCI controller on e0100000.sdhci [e0100000.sdhci] using ADMA
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
TCP: cubic registered
NET: Registered protocol family 17
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
Registering SWP/SWPB emulation handler
/home/x/project/x/zynq/petalinux-v2015.4-final/components/linux-kernel/xlnx-4.0/drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
ALSA device list:
No soundcards found.
Freeing unused kernel memory: 5004K (c0661000 - c0b44000)
mmc0: new high speed SDHC card at address 0007
mmcblk0: mmc0:0007 DDINC 7.42 GiB
mmcblk0: p1
random: dd urandom read with 1 bits of entropy available
NET: Registered protocol family 10
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Device tree
system-top-dts:
/dts-v1/;
/include/ "system-conf.dtsi"
/ {
};
system-conf.dtsi:
/*
* CAUTION: This file is automatically generated by PetaLinux SDK.
* DO NOT modify this file
*/
/include/ "skeleton.dtsi"
/include/ "zynq-7000.dtsi"
/include/ "pcw.dtsi"
/include/ "pl.dtsi"
/ {
tmodel = "Mini-ITX-Zedboard-UWBRx-v2";
taliases {
ttserial0 = &uart1;
ttethernet0 = &gem0;
ttspi0 = &qspi;
t};
tchosen {
ttbootargs = "console=ttyPS0,115200 earlyprintk";
t};
tmemory {
ttdevice_type = "memory";
ttreg = <0x0 0x40000000>;
t};
};
&gem0 {
tlocal-mac-address = [00 0a 35 00 1e 53];
};
&qspi {
t#address-cells = <1>;
t#size-cells = <0>;
tflash0: flash@0 {
ttcompatible = "micron,n25q128";
ttreg = <0x0>;
tt#address-cells = <1>;
tt#size-cells = <1>;
ttspi-max-frequency = <50000000>;
ttpartition@0x00000000 {
tttlabel = "boot";
tttreg = <0x00000000 0x00500000>;
tt};
ttpartition@0x00500000 {
tttlabel = "bootenv";
tttreg = <0x00500000 0x00020000>;
tt};
ttpartition@0x00520000 {
tttlabel = "kernel";
tttreg = <0x00520000 0x00a80000>;
tt};
ttpartition@0x00fa0000 {
tttlabel = "spare";
tttreg = <0x00fa0000 0x00000000>;
tt};
t};
};
zynq-7000.dtsi:
/*
* Copyright (C) 2011 - 2014 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/include/ "skeleton.dtsi"
/ {
tcompatible = "xlnx,zynq-7000";
tcpus {
tt#address-cells = <1>;
tt#size-cells = <0>;
ttcpu@0 {
tttcompatible = "arm,cortex-a9";
tttdevice_type = "cpu";
tttreg = <0>;
tttclocks = <&clkc 3>;
tttclock-latency = <1000>;
tttcpu0-supply = <®ulator_vccpint>;
tttoperating-points = <
tttt/* kHz uV */
tttt666667 1000000
tttt333334 1000000
ttt>;
tt};
ttcpu@1 {
tttcompatible = "arm,cortex-a9";
tttdevice_type = "cpu";
tttreg = <1>;
tttclocks = <&clkc 3>;
tt};
t};
tpmu {
ttcompatible = "arm,cortex-a9-pmu";
ttinterrupts = <0 5 4>, <0 6 4>;
ttinterrupt-parent = <&intc>;
ttreg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
t};
tregulator_vccpint: fixedregulator@0 {
ttcompatible = "regulator-fixed";
ttregulator-name = "VCCPINT";
ttregulator-min-microvolt = <1000000>;
ttregulator-max-microvolt = <1000000>;
ttregulator-boot-on;
ttregulator-always-on;
t};
tamba: amba {
ttcompatible = "simple-bus";
tt#address-cells = <1>;
tt#size-cells = <1>;
ttinterrupt-parent = <&intc>;
ttranges;
ttadc: adc@f8007100 {
tttcompatible = "xlnx,zynq-xadc-1.00.a";
tttreg = <0xf8007100 0x20>;
tttinterrupts = <0 7 4>;
tttinterrupt-parent = <&intc>;
tttclocks = <&clkc 12>;
tt};
ttcan0: can@e0008000 {
tttcompatible = "xlnx,zynq-can-1.0";
tttstatus = "disabled";
tttclocks = <&clkc 19>, <&clkc 36>;
tttclock-names = "can_clk", "pclk";
tttreg = <0xe0008000 0x1000>;
tttinterrupts = <0 28 4>;
tttinterrupt-parent = <&intc>;
ttttx-fifo-depth = <0x40>;
tttrx-fifo-depth = <0x40>;
tt};
ttcan1: can@e0009000 {
tttcompatible = "xlnx,zynq-can-1.0";
tttstatus = "disabled";
tttclocks = <&clkc 20>, <&clkc 37>;
tttclock-names = "can_clk", "pclk";
tttreg = <0xe0009000 0x1000>;
tttinterrupts = <0 51 4>;
tttinterrupt-parent = <&intc>;
ttttx-fifo-depth = <0x40>;
tttrx-fifo-depth = <0x40>;
tt};
ttgpio0: gpio@e000a000 {
tttcompatible = "xlnx,zynq-gpio-1.0";
ttt#gpio-cells = <2>;
tttclocks = <&clkc 42>;
tttgpio-controller;
tttinterrupt-parent = <&intc>;
tttinterrupts = <0 20 4>;
tttreg = <0xe000a000 0x1000>;
tt};
tti2c0: i2c@e0004000 {
tttcompatible = "cdns,i2c-r1p10";
tttstatus = "disabled";
tttclocks = <&clkc 38>;
tttinterrupt-parent = <&intc>;
tttinterrupts = <0 25 4>;
tttreg = <0xe0004000 0x1000>;
ttt#address-cells = <1>;
ttt#size-cells = <0>;
tt};
tti2c1: i2c@e0005000 {
tttcompatible = "cdns,i2c-r1p10";
tttstatus = "disabled";
tttclocks = <&clkc 39>;
tttinterrupt-parent = <&intc>;
tttinterrupts = <0 48 4>;
tttreg = <0xe0005000 0x1000>;
ttt#address-cells = <1>;
ttt#size-cells = <0>;
tt};
ttintc: interrupt-controller@f8f01000 {
tttcompatible = "arm,cortex-a9-gic";
ttt#interrupt-cells = <3>;
tttinterrupt-controller;
tttreg = <0xF8F01000 0x1000>,
ttt <0xF8F00100 0x100>;
tt};
ttL2: cache-controller@f8f02000 {
tttcompatible = "arm,pl310-cache";
tttreg = <0xF8F02000 0x1000>;
tttinterrupts = <0 2 4>;
tttarm,data-latency = <3 2 2>;
tttarm,tag-latency = <2 2 2>;
tttcache-unified;
tttcache-level = <2>;
tt};
ttmc: memory-controller@f8006000 {
tttcompatible = "xlnx,zynq-ddrc-a05";
tttreg = <0xf8006000 0x1000>;
tt};
ttocmc: ocmc@f800c000 {
tttcompatible = "xlnx,zynq-ocmc-1.0";
tttinterrupt-parent = <&intc>;
tttinterrupts = <0 3 4>;
tttreg = <0xf800c000 0x1000>;
tt};
ttuart0: serial@e0000000 {
tttcompatible = "xlnx,xuartps", "cdns,uart-r1p8";
tttstatus = "disabled";
tttclocks = <&clkc 23>, <&clkc 40>;
tttclock-names = "uart_clk", "pclk";
tttreg = <0xE0000000 0x1000>;
tttinterrupts = <0 27 4>;
tt};
ttuart1: serial@e0001000 {
tttcompatible = "xlnx,xuartps", "cdns,uart-r1p8";
tttstatus = "disabled";
tttclocks = <&clkc 24>, <&clkc 41>;
tttclock-names = "uart_clk", "pclk";
tttreg = <0xE0001000 0x1000>;
tttinterrupts = <0 50 4>;
tt};
ttspi0: spi@e0006000 {
tttcompatible = "xlnx,zynq-spi-r1p6";
tttreg = <0xe0006000 0x1000>;
tttstatus = "disabled";
tttinterrupt-parent = <&intc>;
tttinterrupts = <0 26 4>;
tttclocks = <&clkc 25>, <&clkc 34>;
tttclock-names = "ref_clk", "pclk";
ttt#address-cells = <1>;
ttt#size-cells = <0>;
tt};
ttspi1: spi@e0007000 {
tttcompatible = "xlnx,zynq-spi-r1p6";
tttreg = <0xe0007000 0x1000>;
tttstatus = "disabled";
tttinterrupt-parent = <&intc>;
tttinterrupts = <0 49 4>;
tttclocks = <&clkc 26>, <&clkc 35>;
tttclock-names = "ref_clk", "pclk";
ttt#address-cells = <1>;
ttt#size-cells = <0>;
tt};
ttqspi: spi@e000d000 {
tttclock-names = "ref_clk", "pclk";
tttclocks = <&clkc 10>, <&clkc 43>;
tttcompatible = "xlnx,zynq-qspi-1.0";
tttstatus = "disabled";
tttinterrupt-parent = <&intc>;
tttinterrupts = <0 19 4>;
tttreg = <0xe000d000 0x1000>;
ttt#address-cells = <1>;
ttt#size-cells = <0>;
tt};
ttsmcc: memory-controller@e000e000 {
ttt#address-cells = <1>;
ttt#size-cells = <1>;
tttstatus = "disabled";
tttclock-names = "memclk", "aclk";
tttclocks = <&clkc 11>, <&clkc 44>;
tttcompatible = "arm,pl353-smc-r2p1";
tttinterrupt-parent = <&intc>;
tttinterrupts = <0 18 4>;
tttranges ;
tttreg = <0xe000e000 0x1000>;
tttnand0: flash@e1000000 {
ttttstatus = "disabled";
ttttcompatible = "arm,pl353-nand-r2p1";
ttttreg = <0xe1000000 0x1000000>;
tttt#address-cells = <0x1>;
tttt#size-cells = <0x1>;
ttt};
tttnor0: flash@e2000000 {
ttttstatus = "disabled";
ttttcompatible = "cfi-flash";
ttttreg = <0xe2000000 0x2000000>;
tttt#address-cells = <1>;
tttt#size-cells = <1>;
ttt};
tt};
ttgem0: ethernet@e000b000 {
tttcompatible = "cdns,gem";
tttreg = <0xe000b000 0x1000>;
tttstatus = "disabled";
tttinterrupts = <0 22 4>;
tttclocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
tttclock-names = "pclk", "hclk", "tx_clk";
ttt#address-cells = <1>;
ttt#size-cells = <0>;
tt};
ttgem1: ethernet@e000c000 {
tttcompatible = "cdns,gem";
tttreg = <0xe000c000 0x1000>;
tttstatus = "disabled";
tttinterrupts = <0 45 4>;
tttclocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
tttclock-names = "pclk", "hclk", "tx_clk";
ttt#address-cells = <1>;
ttt#size-cells = <0>;
tt};
ttsdhci0: sdhci@e0100000 {
tttcompatible = "arasan,sdhci-8.9a";
tttstatus = "disabled";
tttclock-names = "clk_xin", "clk_ahb";
tttclocks = <&clkc 21>, <&clkc 32>;
tttinterrupt-parent = <&intc>;
tttinterrupts = <0 24 4>;
tttreg = <0xe0100000 0x1000>;
tt};
ttsdhci1: sdhci@e0101000 {
tttcompatible = "arasan,sdhci-8.9a";
tttstatus = "disabled";
tttclock-names = "clk_xin", "clk_ahb";
tttclocks = <&clkc 22>, <&clkc 33>;
tttinterrupt-parent = <&intc>;
tttinterrupts = <0 47 4>;
tttreg = <0xe0101000 0x1000>;
tt};
ttslcr: slcr@f8000000 {
ttt#address-cells = <1>;
ttt#size-cells = <1>;
tttcompatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
tttreg = <0xF8000000 0x1000>;
tttranges;
tttclkc: clkc@100 {
tttt#clock-cells = <1>;
ttttcompatible = "xlnx,ps7-clkc";
ttttfclk-enable = <0xf>;
ttttclock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
tttttt"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
tttttt"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
tttttt"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
tttttt"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
tttttt"dma", "usb0_aper", "usb1_aper", "gem0_aper",
tttttt"gem1_aper", "sdio0_aper", "sdio1_aper",
tttttt"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
tttttt"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
tttttt"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
tttttt"dbg_trc", "dbg_apb";
ttttreg = <0x100 0x100>;
ttt};
tttpinctrl0: pinctrl@700 {
ttttcompatible = "xlnx,pinctrl-zynq";
ttttreg = <0x700 0x200>;
ttttsyscon = <&slcr>;
ttt};
tt};
ttdmac_s: dmac@f8003000 {
tttcompatible = "arm,pl330", "arm,primecell";
tttreg = <0xf8003000 0x1000>;
tttinterrupt-parent = <&intc>;
tttinterrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
tttt"dma4", "dma5", "dma6", "dma7";
tttinterrupts = <0 13 4>,
ttt <0 14 4>, <0 15 4>,
ttt <0 16 4>, <0 17 4>,
ttt <0 40 4>, <0 41 4>,
ttt <0 42 4>, <0 43 4>;
ttt#dma-cells = <1>;
ttt#dma-channels = <8>;
ttt#dma-requests = <4>;
tttclocks = <&clkc 27>;
tttclock-names = "apb_pclk";
tt};
ttdevcfg: devcfg@f8007000 {
tttclock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
tttclocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
tttcompatible = "xlnx,zynq-devcfg-1.0";
tttinterrupt-parent = <&intc>;
tttinterrupts = <0 8 4>;
tttreg = <0xf8007000 0x100>;
tttsyscon = <&slcr>;
tt};
ttglobal_timer: timer@f8f00200 {
tttcompatible = "arm,cortex-a9-global-timer";
tttreg = <0xf8f00200 0x20>;
tttinterrupts = <1 11 0x301>;
tttinterrupt-parent = <&intc>;
tttclocks = <&clkc 4>;
tt};
ttttc0: timer@f8001000 {
tttinterrupt-parent = <&intc>;
tttinterrupts = <0 10 4>, <0 11 4>, <0 12 4>;
tttcompatible = "cdns,ttc";
tttclocks = <&clkc 6>;
tttreg = <0xF8001000 0x1000>;
tt};
ttttc1: timer@f8002000 {
tttinterrupt-parent = <&intc>;
tttinterrupts = <0 37 4>, <0 38 4>, <0 39 4>;
tttcompatible = "cdns,ttc";
tttclocks = <&clkc 6>;
tttreg = <0xF8002000 0x1000>;
tt};
ttscutimer: timer@f8f00600 {
tttinterrupt-parent = <&intc>;
tttinterrupts = <1 13 0x301>;
tttcompatible = "arm,cortex-a9-twd-timer";
tttreg = <0xf8f00600 0x20>;
tttclocks = <&clkc 4>;
tt};
ttusb0: usb@e0002000 {
tttcompatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
tttstatus = "disabled";
tttclocks = <&clkc 28>;
tttinterrupt-parent = <&intc>;
tttinterrupts = <0 21 4>;
tttreg = <0xe0002000 0x1000>;
tttphy_type = "ulpi";
tt};
ttusb1: usb@e0003000 {
tttcompatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
tttstatus = "disabled";
tttclocks = <&clkc 29>;
tttinterrupt-parent = <&intc>;
tttinterrupts = <0 44 4>;
tttreg = <0xe0003000 0x1000>;
tttphy_type = "ulpi";
tt};
ttwatchdog0: watchdog@f8005000 {
tttclocks = <&clkc 45>;
tttcompatible = "cdns,wdt-r1p2";
tttinterrupt-parent = <&intc>;
tttinterrupts = <0 9 1>;
tttreg = <0xf8005000 0x1000>;
ttttimeout-sec = <10>;
tt};
t};
};
pcw.dtsi:
/*
* CAUTION: This file is automatically generated by Xilinx.
* Version: HSI 2015.4
* Today is: Tue Mar 8 09:09:30 2016
*/
/ {
tcpus {
ttcpu@0 {
tttoperating-points = <666666 1000000 333333 1000000>;
tt};
t};
};
&gem0 {
tenet-reset = <&gpio0 47 0>;
tphy-mode = "rgmii-id";
tstatus = "okay";
txlnx,ptp-enet-clock = <0x69f6bcb>;
};
&gpio0 {
temio-gpio-width = <64>;
tgpio-mask-high = <0x0>;
tgpio-mask-low = <0x5600>;
};
&i2c0 {
tclock-frequency = <400000>;
ti2c-reset = <&gpio0 46 0>;
tstatus = "okay";
};
&intc {
tnum_cpus = <2>;
tnum_interrupts = <96>;
};
&qspi {
tis-dual = <1>;
tnum-cs = <1>;
tstatus = "okay";
};
&sdhci0 {
tstatus = "okay";
txlnx,has-cd = <0x1>;
txlnx,has-power = <0x0>;
txlnx,has-wp = <0x1>;
};
&uart1 {
tcurrent-speed = <115200>;
tdevice_type = "serial";
tport-number = <0>;
tstatus = "okay";
};
&usb0 {
tdr_mode = "host";
tphy_type = "ulpi";
tstatus = "okay";
tusb-reset = <&gpio0 7 0>;
};
&clkc {
tfclk-enable = <0x1>;
tps-clk-frequency = <33333333>;
};
Hope someone can give me a hint
Best Regards
Bob
