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Zynq 7100 PS lockup

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It appears that when I get to a certain utilization of the Z7100 device in the PL it will cause the PS to lockup where I cannot get access to the PS through the serial port.  I do see that the logic in the PL is still running using the Vivado Logic analyzer to probe some of the signals.  When I removed 20,000 LUTs then the issue goes away.  I did find a post that seems to be very similar issue I am having. "ps-freezes-when-making-use-pl"

 

I was wondering if there is any other information on this issue?

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    Hello,

     

    I believe I'm hitting the same problem. Is there any progress?

     

    In my case I have a design using large amount of resources (DSPs and BRAMs) and all 4 AXI-HP channels. The design meets timing at 200Mhz.

    The software is a very simple bare-metal app. It just sets bit in register to start operation and  waits for completion. I've added code to reprogram FPGA clock divisor value in software.

    At 50Mhz or 66Mhz everything works fine.

    At 100Mhz I start seeing occasional random glitches in the data, located mostly towards the end of computation.

    At 200Mhz the PS either locks up or dies completely, dropping JTAG connection.

    While investigating the issue I set a pair of HW breakpoints, just before and just after writing '1' to register to start the operation. When (if) it stops at the second breakpoint I see the entire content of memory suddenly changing and it appears that entire memory subsystem is stuffed up, for example writing to memory using "mwr" in XSCT console has no effect or causes random changes in wrong memory locations(!).

    I do have AXI protocol checkers and  chipscope connected to all AXI busses and everything looks OK on the PL side (when it works).

     

    I now strongly suspect it being a power supply issue. I see these kinds of spikes on the power supply voltage (that's running a 66Mhz or 3 times slower than the target):

    image

    [ Inserting picture does not seem to work, image url is: https://preview.ibb.co/maTUhR/power.png ]

     

    I appreciate any help,

    Regards,

    Dmitri

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  • 0

    Hello,

     

    I believe I'm hitting the same problem. Is there any progress?

     

    In my case I have a design using large amount of resources (DSPs and BRAMs) and all 4 AXI-HP channels. The design meets timing at 200Mhz.

    The software is a very simple bare-metal app. It just sets bit in register to start operation and  waits for completion. I've added code to reprogram FPGA clock divisor value in software.

    At 50Mhz or 66Mhz everything works fine.

    At 100Mhz I start seeing occasional random glitches in the data, located mostly towards the end of computation.

    At 200Mhz the PS either locks up or dies completely, dropping JTAG connection.

    While investigating the issue I set a pair of HW breakpoints, just before and just after writing '1' to register to start the operation. When (if) it stops at the second breakpoint I see the entire content of memory suddenly changing and it appears that entire memory subsystem is stuffed up, for example writing to memory using "mwr" in XSCT console has no effect or causes random changes in wrong memory locations(!).

    I do have AXI protocol checkers and  chipscope connected to all AXI busses and everything looks OK on the PL side (when it works).

     

    I now strongly suspect it being a power supply issue. I see these kinds of spikes on the power supply voltage (that's running a 66Mhz or 3 times slower than the target):

    image

    [ Inserting picture does not seem to work, image url is: https://preview.ibb.co/maTUhR/power.png ]

     

    I appreciate any help,

    Regards,

    Dmitri

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