Kevin Keryk wrote to me recently (2/16/2021) on a query I asked on github, so I am following his advice and creating a topic for general discussion in this forum, and I will post any Xilinx board definition file that comes out of the discussin process. Kevin, I will try to close that ticket (#8) with a link to this thread. Thanks. N3RDX
My best recommendation for learning the Xilinx tools and for a well maintained Pmod example design/tutorial from the ground up is the one found in the Avnet MiniZed Technical Training Course (TTC) on Hackster.io Workshops which is currently available for free:
It was last updated for 2019.1 tools but it uses an Digital Humidity and Temperature Sensor Pmod which should be a good place to start for testing a known working example design:
The 12-pin Pmod connector format only provides 8 IOs for your design as 2 pins are reserved for 3.3V power and 2 pins are reserved for ground. You can find out more about the Pmod specification on the Digilent website:
As for dividing up the sub-connectors, this topic comes up periodically but due to lack of consensus on how to approach this in a manner that would make everyone happy, we decided to leave this open ended an allow the community to assign XDC constraints from the master constraints file as needed. You could try to follow the Digilent specification which would maximize the compatibility of your approach across all of the Pmod variants and interpretations of the specification you might find in the wild.
For PCIe, you would need to use Gigabit transceivers which some devices in the Zynq-7000 family have, but the ZC7007S device on MiniZed does not. However, all the Zynq-7000 family of devices do have IO pins which can be configured in differential mode so that you can run higher speed signaling such as LVDS or TMDS type signals over these pairs.
Here you can see that the pairs have been marked with _P and _N suffixes to denote which signal supports a positive swing and which supports a negative swing. For example, PMOD1_D0_P and PMOD1_D0_N would constitute a differential pair. The signal routes within a pair are length matched traces within a certain tolerance and the pairs themselves for each connector are group length matched within another tolerance so that you can expect all signals to arrive at the destination within a certain period of time.
There is an LVDS display example that we had years ago, which is no longer maintained due to lack of community interest, which showed how to abuse the Pmod interface and implement an RGBA/B panel interface using LVDS transmission. So yes, you can theoretically achieve higher speeds over Pmod but there is some practical speed limit before you need to start looking at a board with an FMC expansion or Gigabit transceiver devices.
I can see that this discussion is extending past the scope of what we can support for Github comments. Perhaps it would be better to migrate the discussion to our MiniZed community forums where the larger community and my other colleagues can provide more input on this?
If it is okay with you, would you please start a new thread on the Element14 MiniZed forum and provide a link to the new thread within this issue tracker so that we can close this issue out and continue the discussion in the public forum?
Again, I really appreciate your willingness to contribute here! It is very exciting when community members expand upon our work and improve things for others to leverage this work!