PL clock Rate

Question

The minized board definition file configures the PL clocks to be:

FCLK_CLK0 - 50Mhz

FCLK_CLK1 - 100Mhz

FCLK_CLK2 - 50Mhz

FCLK_CLK3 - 50Mhz

Can FCLK_CLK0 be changed to 250Mhz? Does all PL IP support this rate?

The reason for asking this, trying to do a Manchester serial decoder that supports 10Mhz, so, trying to find the start bit requires a 16x clock. So, thought why not support the max ;)

jafoste4 · Accepted Answer

Hello tmichals,

Those PL clocks support .1MHz - 250MHz clock speeds.

I am sure some support that rate and some do not. Please look at the datasheet for whatever PL IP you wish to use to determine this.

--Josh