For my application, I set FCLK_CLK3 to 5 MHz in Vivado. This clock is not activated in the default BSP provided by Avnet for Minized. When I run a bare metal application, it works perfect without any problem, however, in Linux application, I get a different frequency. My calculations show that it is set to 66.67 MHz.
Based on what I have read in Xilinx Forum, the FPGA clock is set by FSBL, however, I don't know why it doesn't set my designated clock frequency. I use Avnet pre-built images along with the rootfs.wic file that I create with the petalinux. To program the FPGA, I am using Petalinux fpgautil.
Does anybody know how to fix this issue or what I am doing wrong here?
Is there any way to check and/or set the PL fabric clock frequency in Linux?