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Data transfer from PL to PS DDR

Waqas

We are using MiniZed Hardware in our project. We want to move some data from PL side to PS DDR through the control of PL side. We are using AXI datamover IP to transfer data from PL to PS DDR. However, we are not able to see any data in PS DDR after PL has provided data on Streaming Interface of AXI datamover IP.

 Can anyone suggest solution to this problem??

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  • On an Altera FPGA design I did a couple of years ago I needed to grab data from a table and load it into the PL from DRAM. I used a built in AXI interface soft macro and coded my own AXI master. Even though simulations worked using a model of the AXI Slave I found, it did not work in hardware.

    I found a better model of an AXI slave and utilized it for my SRAM model of the DDR. Then I debugged some of my AXI signal timing. There was an error, but even though the simulation worked after I fixed my bugs, the real hardware still did not.

    Then the FAE I worked with reminded me that there is a minimum burst length requirement for the DDR interface and the DDR AXI slave will ignore any reads that are too short. I can't remember the minimum, but you can probably find it in the ARM documentation for the CPU you are using.

    I added SRAM cache to my design and changed the burst to be sixteen 32 bit words and then the real hardware started working.

    I suggest you setup a test bench and make sure your timing is correct. If you used a soft macro that is known to work, and simulation works, try increasing your burst length.

    This is all I know about the voodoo of AXI DRAM interfaces.

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  • On an Altera FPGA design I did a couple of years ago I needed to grab data from a table and load it into the PL from DRAM. I used a built in AXI interface soft macro and coded my own AXI master. Even though simulations worked using a model of the AXI Slave I found, it did not work in hardware.

    I found a better model of an AXI slave and utilized it for my SRAM model of the DDR. Then I debugged some of my AXI signal timing. There was an error, but even though the simulation worked after I fixed my bugs, the real hardware still did not.

    Then the FAE I worked with reminded me that there is a minimum burst length requirement for the DDR interface and the DDR AXI slave will ignore any reads that are too short. I can't remember the minimum, but you can probably find it in the ARM documentation for the CPU you are using.

    I added SRAM cache to my design and changed the burst to be sixteen 32 bit words and then the real hardware started working.

    I suggest you setup a test bench and make sure your timing is correct. If you used a soft macro that is known to work, and simulation works, try increasing your burst length.

    This is all I know about the voodoo of AXI DRAM interfaces.

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