Actions
Forum Thread Details
  • Replies 1 reply
  • Subscribers 267 subscribers
  • Views 466 views
  • Users 0 members are here
Related

Picozed - XC7z030 VCCO Supply sequencing

santu17

Is it mandatory to provide VCCO (HP & HR Banks ) voltages simultaneously?

 

HP Banks operate at 1.8V & HR Banks operate at 3.3V. I've provided the VCCO voltages from TLV62130(1.8V & 3.3V) & it follows the default power sequencing of 1.8V->1.5V->3.3V.

 

Will this cause any issues? I'm not interfacing any FMC/PCIE with this so can't use separate dual output regulators for this purpose considering the low power consumption of VCCO( 0.2-0.3A).

Parents

  • As long as you have brought up VCCINT, VCCBRAM, VCCAUX, and VCCAUX_IO first, then the VCCO supplies can come up in any order. However, you do need to be cautious with the HR supply of 3.3V. See this statement in Xilinx DS191:

     

    For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0:

    • The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels.

    • The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.

     

    Bryan

Reply

  • As long as you have brought up VCCINT, VCCBRAM, VCCAUX, and VCCAUX_IO first, then the VCCO supplies can come up in any order. However, you do need to be cautious with the HR supply of 3.3V. See this statement in Xilinx DS191:

     

    For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0:

    • The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels.

    • The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.

     

    Bryan

Children
No Data