Hi folks,
Thinking I've encountered a concern regarding the routing of the Rx Clock on the Ethernet PHY on the PicoZed FMCC Carrier Card, and wanting to turn it over to some other eyes to confirm or refute.
I'm preparing to use the Carrier Card to prototype a gigabit ethernet connection driven by logic on the Zynq PL of a PicoZed card, instantiating the AXI Ethernet Block (R6.2). (Need to support jumbo frames, which precludes using a MAC of the PS.)
From the schematics of PicoZed and FMCC carrier, I trace the RXC receive channel clock of the Marvell PHY on the carrier through JX2 pin 94 to pad V11 of the Zynq 7020. But since V11 is not an MRCC or SRCC pin, Vivado (rightfully, I believe) complains vociferously at its inability to successfully route the design.
On further study of the schematics, I find the a nearby JX2 connector pin 74, which does route to an SRCC pin, in the same I/O bank 13 as the other signals of the PHY interface. It is labeled IO_L14P_T2_SRCC_13 on the Zynq, bonded to pad Y9, and makes the implementation tools much much happier.
But before I turn the carrier card over to our tech folks for the minor surgery needed to reroute the PHY's RXC output through JX2.74, I thought I'd check with the group to see if anyone could confirm (or otherwise comment upon) both:
1) my reading of the documentation; and
2) its accuracy.
In case it matters, the carrier card I have is labeled MBCC-PZCC-PCB-C, 1450043.
Many thanks,
Joseph
