Actions
Forum Thread Details
  • State Not Answered
  • Replies 11 replies
  • Subscribers 339 subscribers
  • Views 1061 views
  • Users 0 members are here
Related

PicoZed / Carrier Ethernet PHY RXC Routing

chailatte

Hi folks,


Thinking I've encountered a concern regarding the routing of the Rx Clock on the Ethernet PHY on the PicoZed FMCC Carrier Card, and wanting to turn it over to some other eyes to confirm or refute.


I'm preparing to use the Carrier Card to prototype a gigabit ethernet connection driven by logic on the Zynq PL of a PicoZed card, instantiating the AXI Ethernet Block (R6.2).  (Need to support jumbo frames, which precludes using a MAC of the PS.)


From the schematics of PicoZed and FMCC carrier, I trace the RXC receive channel clock of the Marvell PHY on the carrier through JX2 pin 94 to pad V11 of the Zynq 7020.  But since V11 is not an MRCC or SRCC pin, Vivado (rightfully, I believe) complains vociferously at its inability to successfully route the design.


On further study of the schematics, I find the a nearby JX2 connector pin 74, which does route to an SRCC pin, in the same I/O bank 13 as the other signals of the PHY interface.  It is labeled IO_L14P_T2_SRCC_13 on the Zynq, bonded to pad Y9, and makes the implementation tools much much happier.


But before I turn the carrier card over to our tech folks for the minor surgery needed to reroute the PHY's RXC output through JX2.74, I thought I'd check with the group to see if anyone could confirm (or otherwise comment upon) both:
1) my reading of the documentation; and
2) its accuracy.


In case it matters, the carrier card I have is labeled MBCC-PZCC-PCB-C, 1450043.


Many thanks,


Joseph

Parents
  • 0

    Is there an example design available for either the external carrier PHY or both PHYs? I have not been able to create a working design using the carrier PHY.

  • 0 in reply to Former Member

    We have a dual Ethernet design that we did with Xilinx in 2014.4. You can request this through your FAE. It used the PS GEM1 through EMIO into PL and a PL shim, then out the PL IO. This passed timing and worked reliably. The only rework required was changing the PHYAD for the PHY on the Carrier to a '1'. The RX_CLK is not a problem with this design.

     

    Creating the 2nd Ethernet interface using a MAC in the PL causes problems. In this case, RX_CLK does need to come in on a clock-capable pin. The only way to accomplish this is by reworking the Carrier. Of course, adding an external wire for your clock is not ideal.

     

    So, if you can make use of PS GEM1, I think this will work. If you need a PL-based MAC, then unfortunately, I think the best advice may be to prototype with another board temporarily until we can get a new PicoZed Carrier to market. One option would be a MicroZed with MicroZed FMC Carrier along with the Opsero Quad GigE FMC Card (www.ethernetfmc.com).

     

    Bryan

  • 0 in reply to bhfletcher

    I am about to try a design using both Ethernet ports and would like to have a look at the above mentioned solution. However I have no idea of how to contact an Avnet FAE to get my hands on it.

Reply Children
No Data