we use a picoZed 7015 and designed a Carrier Card for it by ourselves. On this carriercard we used the powersupply circuit used in the FMC-V2 CarrierCard.
It’s not possible for us to connect Vivado to the picoZed using JTAG communication. Everytime we try to connect to the target, Vivado shuts down the whole task.
The JTAG port is conneted over the Digilent JTAG-HS2 Programming Cable. When using the programming software "Adapt" of digilent, the FPGA appears at the toolchain, but the ARM doesn’t. When we connect the picoZed in standalone mode over JTAG. Both, ARM Core and FPGA are visible in the Toolchain. Also Vivado doesn’t crash when using picoZed in Standalone Mode, but two errors occur which say “[Labtools 27-2269] No devices detected on target localhost:3121…” and “[Labtools 27-55] Invalid index 0 passed to getIndex”.
We also measured the PG_Module Signal which is Active High when the picoZed is in standalone configuration and the PG_Module Signal on the Carriercard is also High when no picoZed is pluged in. But if the picoZed is connected to the Carriercard the PG_Module Signal turns low. Therefore we found the Design Advisory AR#63149 (https://www.xilinx.com/support/answers/63149.html) and made the recommended test measurement. According to the test results, the PS_POR_B turns high in the calculated Secure Lockdown Window.
Figure 1: PS_POR_B timing calculations
According to this there is the possible risk that the secure lockdown occurs in the time window. So we made the required measurements which are depictured below.
VCCInt vs. PS_POR_B:
Figure 2: Measurement of VCCInt vs. PS_POR_B Tslw=31,25ms
VCCAux vs. PS_POR_B:
Figure 3:VCCAux vs. PS_POR_B Tslw=28.3ms
VCCO_0 vs. PS_POR_B:
Figure 4: VCC0 vs. PS_POR_B Tslw=25.15ms
VCCO_34 vs. PS_POR_B:
Figure 5: VCCO_34 vs. PS_POR_B Tslw=27.5ms
VCCO_13 vs. PS_POR_B:
Figure 6: VCCO_13 vs. PS_POR_B Tslw=23.55ms
INIT_N vs. PS_POR_B:
Figure 7: INIT_N doesn’t turn low after PS_POR_B turns high
All the measurments show the described behavior in the Answer Record (#63149).
We tried to tie a capacitance of 100µF to the PG_Module port at the Carriercard to change the timing between the last PL power ramp and the PS_POR_B. Like shown in Figure 8 the voltage at the PS_POR_B port then rises slowly and drops down from ~1.2V back to LOW after more than 70ms (out of SL-Window range).
Figure 8: VVCO_0 vs. PS_POR_B with a 100μF Capacitance tied from PG_Module to GND
So it still doesn't work. Does anybody have a possible solution to this issue. What can we do?
Thanks for your help!
EDIT: Picture Upload didn't work, so I uploaded them on an extern provider an inserted the links here.