Porting Python 1300 ref design on SVDK: Artifact on image

Hello Ben,

Based on this Xilinx Community Forum post it looks like you found the issue to be the xdc file:

http://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Porting-HDMI-python1300-ref-design-on-SVDK-No-valid-object-s/td-p/651248

-Gary

Ben,

Could you share the working XDC file for the SVDK, for the benefit of the community ?

Thanks in advance,

Regards,

Mario.

Hello,

Sorry I just realize that forgot to answer.
Here is the xdc:

########################
# Physical Constraints #
########################

# HDMI Output (ADV7511) on Embedded Vision Carrier Card
set_property IOSTANDARD LVCMOS25 [get_ports {IO_HDMIO_data[15]}]
set_property IOSTANDARD LVCMOS25 [get_ports {IO_HDMIO_data[14]}]
set_property IOSTANDARD LVCMOS25 [get_ports {IO_HDMIO_data[13]}]
set_property IOSTANDARD LVCMOS25 [get_ports {IO_HDMIO_data[12]}]
set_property IOSTANDARD LVCMOS25 [get_ports {IO_HDMIO_data[11]}]
set_property IOSTANDARD LVCMOS25 [get_ports {IO_HDMIO_data[10]}]
set_property IOSTANDARD LVCMOS25 [get_ports {IO_HDMIO_data[9]}]
set_property IOSTANDARD LVCMOS25 [get_ports {IO_HDMIO_data[8]}]
set_property IOSTANDARD LVCMOS25 [get_ports {IO_HDMIO_data[7]}]
set_property IOSTANDARD LVCMOS25 [get_ports {IO_HDMIO_data[6]}]
set_property IOSTANDARD LVCMOS25 [get_ports {IO_HDMIO_data[5]}]
set_property IOSTANDARD LVCMOS25 [get_ports {IO_HDMIO_data[4]}]
set_property IOSTANDARD LVCMOS25 [get_ports {IO_HDMIO_data[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {IO_HDMIO_data[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {IO_HDMIO_data[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {IO_HDMIO_data[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports IO_HDMIO_clk]
set_property IOSTANDARD LVCMOS25 [get_ports IO_HDMIO_spdif]
set_property PACKAGE_PIN W13 [get_ports IO_HDMIO_clk]
set_property PACKAGE_PIN V18 [get_ports IO_HDMIO_spdif]
set_property PACKAGE_PIN Y18 [get_ports {IO_HDMIO_data[15]}]
set_property PACKAGE_PIN Y19 [get_ports {IO_HDMIO_data[14]}]
set_property PACKAGE_PIN AA11 [get_ports {IO_HDMIO_data[13]}]
set_property PACKAGE_PIN AB11 [get_ports {IO_HDMIO_data[12]}]
set_property PACKAGE_PIN V11 [get_ports {IO_HDMIO_data[11]}]
set_property PACKAGE_PIN W11 [get_ports {IO_HDMIO_data[10]}]
set_property PACKAGE_PIN W12 [get_ports {IO_HDMIO_data[9]}]
set_property PACKAGE_PIN V15 [get_ports {IO_HDMIO_data[8]}]
set_property PACKAGE_PIN W15 [get_ports {IO_HDMIO_data[7]}]
set_property PACKAGE_PIN AA16 [get_ports {IO_HDMIO_data[6]}]
set_property PACKAGE_PIN AA17 [get_ports {IO_HDMIO_data[5]}]
set_property PACKAGE_PIN Y12 [get_ports {IO_HDMIO_data[4]}]
set_property PACKAGE_PIN Y13 [get_ports {IO_HDMIO_data[3]}]
set_property PACKAGE_PIN V13 [get_ports {IO_HDMIO_data[2]}]
set_property PACKAGE_PIN V14 [get_ports {IO_HDMIO_data[1]}]
set_property PACKAGE_PIN R17 [get_ports {IO_HDMIO_data[0]}]

# PYTHON-1300 Camera Module
set_property PACKAGE_PIN J5 [get_ports {IO_PYTHON_CAM_trigger[0]}]
set_property PACKAGE_PIN R3 [get_ports {IO_PYTHON_CAM_trigger[1]}]
set_property PACKAGE_PIN T1 [get_ports {IO_PYTHON_CAM_trigger[2]}]
set_property PACKAGE_PIN J7 [get_ports IO_PYTHON_CAM_reset_n]
set_property PACKAGE_PIN J6 [get_ports IO_PYTHON_SPI_spi_mosi]
set_property PACKAGE_PIN M7 [get_ports IO_PYTHON_SPI_spi_sclk]
set_property PACKAGE_PIN K8 [get_ports IO_PYTHON_SPI_spi_ssel_n]
set_property PACKAGE_PIN P6 [get_ports {IO_PYTHON_CAM_data_p[0]}]
set_property PACKAGE_PIN R5 [get_ports {IO_PYTHON_CAM_data_p[1]}]
set_property PACKAGE_PIN L6 [get_ports {IO_PYTHON_CAM_data_p[2]}]
set_property PACKAGE_PIN L5 [get_ports {IO_PYTHON_CAM_data_p[3]}]
set_property PACKAGE_PIN R2 [get_ports {IO_PYTHON_CAM_monitor[0]}]
set_property PACKAGE_PIN T2 [get_ports {IO_PYTHON_CAM_monitor[1]}]
set_property PACKAGE_PIN U2 [get_ports IO_PYTHON_CAM_clk_out_p]
set_property PACKAGE_PIN M8 [get_ports IO_PYTHON_CAM_clk_pll]
set_property PACKAGE_PIN J8 [get_ports IO_PYTHON_SPI_spi_miso]
set_property PACKAGE_PIN L2 [get_ports IO_PYTHON_CAM_sync_p]

set_property IOSTANDARD LVCMOS25 [get_ports {IO_PYTHON_CAM_trigger[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {IO_PYTHON_CAM_trigger[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {IO_PYTHON_CAM_trigger[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports IO_PYTHON_CAM_reset_n]
set_property IOSTANDARD LVCMOS25 [get_ports IO_PYTHON_SPI_spi_mosi]
set_property IOSTANDARD LVCMOS25 [get_ports IO_PYTHON_SPI_spi_sclk]
set_property IOSTANDARD LVCMOS25 [get_ports IO_PYTHON_SPI_spi_ssel_n]
set_property IOSTANDARD LVDS_25 [get_ports {IO_PYTHON_CAM_data_p[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {IO_PYTHON_CAM_data_p[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {IO_PYTHON_CAM_data_p[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {IO_PYTHON_CAM_data_p[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {IO_PYTHON_CAM_monitor[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {IO_PYTHON_CAM_monitor[0]}]
set_property IOSTANDARD LVDS_25 [get_ports IO_PYTHON_CAM_clk_out_p]
set_property IOSTANDARD LVCMOS25 [get_ports IO_PYTHON_CAM_clk_pll]
set_property IOSTANDARD LVCMOS25 [get_ports IO_PYTHON_SPI_spi_miso]
set_property IOSTANDARD LVDS_25 [get_ports IO_PYTHON_CAM_sync_p]

set_property DIFF_TERM TRUE [get_ports {IO_PYTHON_CAM_data_p[0]}]
set_property DIFF_TERM TRUE [get_ports {IO_PYTHON_CAM_data_p[1]}]
set_property DIFF_TERM TRUE [get_ports {IO_PYTHON_CAM_data_p[2]}]
set_property DIFF_TERM TRUE [get_ports {IO_PYTHON_CAM_data_p[3]}]
set_property DIFF_TERM TRUE [get_ports IO_PYTHON_CAM_sync_p]
set_property DIFF_TERM TRUE [get_ports IO_PYTHON_CAM_clk_out_p]

#GPIO to set DE/Hsyhnc/Vsync to ground on SVDK
set_property PACKAGE_PIN V16 [get_ports {gpio_0_tri_io[2]}]
set_property PACKAGE_PIN W16 [get_ports {gpio_0_tri_io[1]}]
set_property PACKAGE_PIN T17 [get_ports {gpio_0_tri_io[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gpio_0_tri_io[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gpio_0_tri_io[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gpio_0_tri_io[0]}]

######################
#  Clock Constraints #
######################

# The following constraints are already created by the "ZYNQ7 Processing System" core
#create_clock -period 13.333 -name clk_fpga_0 [get_nets -hierarchical FCLK_CLK0]
#create_clock -period  6.667 -name clk_fpga_1 [get_nets -hierarchical FCLK_CLK1]
#create_clock -period  5.000 -name clk_fpga_2 [get_nets -hierarchical FCLK_CLK2]
#Ref_design_clk_wiz_0_0
create_clock -period 3.703 -name vita_ser_clk [get_ports IO_PYTHON_CAM_clk_out_p]

# Define asynchronous clock domains
set_clock_groups -asynchronous  -group [get_clocks clk_fpga_0]
                                -group [get_clocks clk_fpga_1]
                                -group [get_clocks clk_out1_Ref_design_clk_wiz_0_0]
                                -group [get_clocks -of [get_pins Ref_design_i/onsemi_python_cam_0/U0/onsemi_vita_cam_v3_1_S00_AXI_inst/onsemi_vita_cam_core_inst/vita_iserdes_v5.vita_iserdes/serdesclockgen[0].ic/gen_no_ls_clk_in.gen_regional_hs_clk_in.gen_multiplier_5.BUFR_regional_hs_clk_in/O]]
                                -group [get_clocks vita_clk]

Br,
Ben

I tried several times to publish my xdc but I get:
"Your comment has been queued for review by site administrators and will be published after approval."
It must be too long and it is impossible to put it as an attachement.
thank for your advice/help
/Ben

Hello Ben,

You original xdc post has been approved and should be visible now. Sorry about the delay, there was no notification that one was pending.

Thanks for sharing!

-Gary