Using GTX transceivers

Many thanks for your reply!

I have been studying the Aurora core using "Aurora 64B/66B v11.2 LogiCORE IP Product Guide". I now have fair understating of the core and I managed to run the simulation successfully with the Aurora example design generated by Vivado using the "Open IP Example Design..."  option. I'm using the core in TX-only Simplex mode for the SMA connectors (MGT1 or GTXE2_X0Y1).

My instantiation of the example design uses two differential clocks: gt_refclk1_p/gt_refclk1_n and init_clk_p/init_clk_n and one singe-ended clock: drp_clk_in. These clocks should be driven from User I/O ports GTXQ0_P, GTXQ0_N, INIT_CLK_P, INIT_CLK_N and DRP_CLK_IN respectively. In the simulation the desired clocks are generated by the testbench aurora_6466b_0_TB but now I'm having trouble to write proper constraints to get this working in real hardware.

It seems that the GTX reference clock is already taken care of in the automatically generated .xdc constraints file: 

   create_clock -period 4.000 [get_ports GTXQ0_P] 

But for the INIT_CLK and the DRP_CLK I have not yet managed to find proper sources. In a design tutorial  "Designing a System Using the Aurora 64B66B Core (Duplex) on the KC705 Evaluation Kit" the INIT_CLK is just connected to pins supplying a 200 MHz differential clock using the LOC command as with the GTXQ0. But my board doesn't have this kind of a clock source. And the reference design doesn't have DRP_CLK at all.

So my question is that where can I get these clocks and how should they be constrained? The differential INIT_CLK should be between 50-200 MHz and the DRP_CLK should be from 50 to x MHz ("where x is device and speed grade dependent." -LogiCORE IP Product Guide). In the IP customize options I now have selected the default values of 50 MHz and 100 MHz for these clocks. I have been trying to genetare the INIT_CLK from the GTXQ0 clock using create_generated_clock command but yet with no luck. It also came to my mind that could I use the Zynq processing system clock FCLK_CLK0 somehow? It might be trivial but I have not yet understood how can I interface with this clock from the constraints file..

I would like to avoid using the IDT programmable clock source offered by the FMC Carrier Card V2 because the final product is only using the PicoZed board.

All the help is much appreciated!
-Jan

Many thanks for your reply!

I have been studying the Aurora core using "Aurora 64B/66B v11.2 LogiCORE IP Product Guide". I now have fair understating of the core and I managed to run the simulation successfully with the Aurora example design generated by Vivado using the "Open IP Example Design..."  option. I'm using the core in TX-only Simplex mode for the SMA connectors (MGT1 or GTXE2_X0Y1).

My instantiation of the example design uses two differential clocks: gt_refclk1_p/gt_refclk1_n and init_clk_p/init_clk_n and one singe-ended clock: drp_clk_in. These clocks should be driven from User I/O ports GTXQ0_P, GTXQ0_N, INIT_CLK_P, INIT_CLK_N and DRP_CLK_IN respectively. In the simulation the desired clocks are generated by the testbench aurora_6466b_0_TB but now I'm having trouble to write proper constraints to get this working in real hardware.

It seems that the GTX reference clock is already taken care of in the automatically generated .xdc constraints file: 

   create_clock -period 4.000 [get_ports GTXQ0_P] 

But for the INIT_CLK and the DRP_CLK I have not yet managed to find proper sources. In a design tutorial  "Designing a System Using the Aurora 64B66B Core (Duplex) on the KC705 Evaluation Kit" the INIT_CLK is just connected to pins supplying a 200 MHz differential clock using the LOC command as with the GTXQ0. But my board doesn't have this kind of a clock source. And the reference design doesn't have DRP_CLK at all.

So my question is that where can I get these clocks and how should they be constrained? The differential INIT_CLK should be between 50-200 MHz and the DRP_CLK should be from 50 to x MHz ("where x is device and speed grade dependent." -LogiCORE IP Product Guide). In the IP customize options I now have selected the default values of 50 MHz and 100 MHz for these clocks. I have been trying to genetare the INIT_CLK from the GTXQ0 clock using create_generated_clock command but yet with no luck. It also came to my mind that could I use the Zynq processing system clock FCLK_CLK0 somehow? It might be trivial but I have not yet understood how can I interface with this clock from the constraints file..

I would like to avoid using the IDT programmable clock source offered by the FMC Carrier Card V2 because the final product is only using the PicoZed board.

All the help is much appreciated!
-Jan