Using GTX transceivers

Question

Hello!

I'm looking for some help how to use the GTX transceivers on PicoZed 7030 board. I'm using the FMC Carrier Card V2 platform and my goal is to send data to one GTX transceiver channel and receive it with another. Later this communication should happen between multiple PicoZed boards.

I currently have a setup where I connect the SMA TX pair to SFP+ module RX pair via SFP+ to SMA adapter. After watching your 4 tutorial videos about how to use IBERT core to validate links I managed to verify that the link is working correctly. The Link was automatically detected by Vivado and it shows the link

MGT_X0Y1/TX (SMA) -> MGT_X0Y2/RX (SFP+)

Status as 6.250 Gbps as expected and no errors.

Now I would want to move to the next step: use the GTX transceivers from a custom logic so that I can send my custom data to one transceiver and receive it to another but I'm really confused how to achieve this. First things I find info about are the "7 Series FPGAs Transceivers Wizard" and "Aurora 64B66B" cores. But when I used the IBERT core I did not need the Transceivers Wizard setup. That makes me want to think that it's not needed.

What I'm looking for is basic steps what is needed to send data from my custom logic to GTX transceiver and receive it back. Do I need transceivers wizard? Do I need to edit .xdc constraints manually? Can I use Aurora example design?

I'm fairly familiar with Vivado and SDK but I have not worked with .xdc constraints. I'm familiar with building a custom AXI4 peripheral.

Best regards
Jan

nahkabiljetti · Accepted Answer

It took some time and experimenting but I now have a working solution with two PicoZed FMC Carrier Card V2 cards connected with optical fibre. I instantiated the Aurora64B66B core with following options:

Line Rate (Gbps): 6.25
GT Refclk (MHz): 250.000
INIT clk (MHz): 50.0
GT DRP clk (MHz): 100.0

Dataflow Mode: Duplex
Interface: Framing
Flow Control: None

DRP Mode: AXI4 Lite

GT Selections:
Lanes: 1
GTXQ0: GTXE2_X0Y2 (SFP+)

Shared Logic:
Include Shared Logic in the core

I then created the example design and used it as a reference to make my own reset and control modules and the constraint file. When I managed to get the channel up (Aurora channel_up signal connected to PL LED) I created a data module writing AXI4 Stream data to the Aurora core via AXI4-Stream Data FIFO. This is because the USER_DATA_S_AXIS_TX interface is clocked by the user_clk_out clock that is asynchronous to the FCLK_CLK0 system clock I use to create the stream. Same thing with receiving the data from the core (USER_DATA_M_AXIS_RX).

For the GT Refclk I used the onboard oscillator generating 250 MHz clock. Init clk and GT DRP clock I took from ZYNQ Processing System FCLK_CLK0 and FCLK_CLK1.