GMII RX Clk pin placement error

Iu2019m running in to an odd pin placement error with the GMII bus with picoZed XC7Z030. This is basically the same working design with microZed XC7Z020. The pinout is for a picoZed carrier FMC network card use the Inrevium TB-FMCL-GLAN-B. This is the same card I have working with Zedboard and microZed. The GMII is connected to the AXI-Ethernet core. Iu2019ve tried several variations on the pinout, but keep running in to placement error:

[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance ZynqIP_i/axi_ethernet_0/eth_mac/U0/tri_mode_ethernet_mac_i/gmii_interface/gmii_rx_clk_ibuf_i at P3 (IOB_X1Y114) since it belongs to a shape containing instance ZynqIP_i/axi_ethernet_0/eth_mac/U0/tri_mode_ethernet_mac_i/gmii_interface/bufio_gmii_rx_clk. The shape requires relative placement between ZynqIP_i/axi_ethernet_0/eth_mac/U0/tri_mode_ethernet_mac_i/gmii_interface/gmii_rx_clk_ibuf_i and ZynqIP_i/axi_ethernet_0/eth_mac/U0/tri_mode_ethernet_mac_i/gmii_interface/bufio_gmii_rx_clk that cannnot be honored because it would result in an invalid location for ZynqIP_i/axi_ethernet_0/eth_mac/U0/tri_mode_ethernet_mac_i/gmii_interface/bufio_gmii_rx_clk. ["C:/Work/Xilinx/HWautofocus/picoZed/picoZedHWAFemacGMIIV1/picoZedHWAFemacGMIIV1.srcs/constrs_1/new/ZynqIP.xdc":325]

Any ideas as to what the problem is?

0 Former Member over 11 years ago

Hello Van,

We will take a look and see what the issue is.

-Gary
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0 Former Member over 11 years ago

I found the problem with GMII RX Clock pin error. The picoZed carrier FMC pinout is not compatible with micorZed carrier FMC pinout. The Rx clock was connected to wrong pin-type. Rx clock needs to be connected to an MRCC or SRCC pin. Iu2019ve fixed the issue with a new GMII pinout, but the pinout wonu2019t work with the Inrevium TB-FMCL-GLAN-B card. Not sure if this is only limited to the XC7Z030 version of picoZed.
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0 Former Member over 11 years ago

The 7010 and 7020 versions of the PicoZed, which share a common PCB, are compatible with the MicroZed Carrier FMC pin out.

As you have determined, the 7030 version of the PicoZed (and the 7015 version which shares a common PCB) are not compatible with the MicroZed Carrier FMC pin out.

We appreciate you bringing this to our attention. We are reviewing the design to determine if changes need to be made to accommodate this.

-Gary
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0 Former Member over 11 years ago

After reviewing the design we decided that the impact of the clocking differences between the 7015/7030 version of the PicoZed and the 7010/7020 PicoZed and the MicroZed does warrant a change. So we will be modifying the 7015/7030 PicoZed design to make the clock capable signal routing compatible with the MicroZed and the 7010/7020 PicoZed.

Once the documents are complete we will post new 'Rev C' PicoZed 7015/7030 documents.

Thanks again for your feedback.

-Gary
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0 100tmiddleton over 8 years ago in reply to Former Member

Hi Gary,
I am running into what I think is the same issue as the original poster. I am using Vivado 2015.4 and am attempting to implement the PL Ethernet Phy using the Tri-Mode EMAC IP Core.
I get the following during implementation:
[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance XXXXXXXX_i/tri_mode_ethernet_mac_0/U0/rgmii_interface/rgmii_rxc_ibuf_i at V11 (IOB_X0Y8) since it belongs to a shape containing instance XXXXXXXX_i/tri_mode_ethernet_mac_0/U0/rgmii_interface/bufio_rgmii_rx_clk. The shape requires relative placement between XXXXXXXX_i/tri_mode_ethernet_mac_0/U0/rgmii_interface/rgmii_rxc_ibuf_i and XXXXXXXX_i/tri_mode_ethernet_mac_0/U0/rgmii_interface/bufio_rgmii_rx_clk that can not be honoured because it would result in an invalid location for XXXXXXXX_i/tri_mode_ethernet_mac_0/U0/rgmii_interface/bufio_rgmii_rx_clk. ["E:/vhdl/XXXXXXXX.srcs/constrs_1/new/PL_Ethernet.xdc":12]

Do you know was this change implemented in the Rev C. version of the 7Z020 PicoZed board? I don't see this as changed with rev C. It looks like the ETH_RX_CLK is connected to JX2.94 on the FMC Carrier (V1) Named BANK13_LVDS_5_P on both B+C versions are connected to pin V11 IO_L21P_T3_DQS_13.
Does this mean I cannot use the Tri-Mode EMAC to connect to the PL Ethernet Phy on the FMC Carrier board?

Regards,
Tom
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0 jafoste4 over 8 years ago

Hello Tom,
If you read Gary's post above, he stated that only the PicoZed 7015/7030 would be affected. So no that was not affected in the PicoZed 7020 B to C version change. Please see the last page of the Schematic for detailed changes between Rev B and Rev C.
http://zedboard.org/sites/default/files/documentations/PicoZed_7010_7020_Rev_C01_Schematic_06252015.pdf
Also try taking a look at this forum post and document.
https://forums.xilinx.com/t5/Networking-and-Connectivity/Critical-Warning-Cannot-set-LOC-property-of-ports/td-p/429440
https://www.xilinx.com/support/documentation/ip_documentation/tri_mode_ethernet_mac/v8_3/pg051-tri-mode-eth-mac.pdf Page 235
--Josh
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