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PCIe End Point Reference Design

drozwood90

Hi there, I wanted to let everyone know that a new design has been posted for the PicoZed 7030 SOM. It is a PCIe End Point Reference Design! It is similar to the design that we provide for the Mini-Module Plus. You can locate this design posted on the PicoZed FMCv2 Carrier Card Reference Design page: http://picozed.org/support/design/13076/106 At this time, we are not able to post the same design for the PicoZed 7015 SOM. There is a slight difference with the internals of the chip and we are having some issues closing timing. We are in contact with Xilinx and are working towards a solution. In the mean time, we have another reference design that is being updated for Vivado 2016.4 and will be posted shortly. As of this post, there is a Vivado 2014.4 version posted. This design is called the PCIe PIO Demo. It uses the PicoZed FMCv1 Carrier Card with either a PicoZed 7015 or a PicoZed 7030 SOM. With a PIN change in the constraints file, it will also run with a PicoZed FMCv2 Carrier Card! You can locate that design under the PicoZed FMCv1 Carrier Card Reference Design page: http://picozed.org/support/design/4701/76 --Dan

  • 0

    Hi Dan,

    Do you have any update for the reference design of 7015 SOM?

    I'm trying to port the reference design of the 7030 SOM for my 7015 SOM board but I miss something, on the FMCv2 Carrier board we have only one lane for TX and one lane for RX but the Reference Design is for 4 lanes.

    Moreover the pin of the Zynq connected to this lanes are the same for 7015 and 7030 (the SOM schematic is the same) but in the .xdc file are connected to other pins.

    Where is my error?

    Thankyou.

  • 0

    Hi alexspin,

    Unfortunately, Xilinx pulled the 7015 from being able to use that IP.  It was getting harder to meet timing with the newer place and route algorithms.

    As for the porting, the 7030 is only 1 lane, so I am not sure why you have 4.  It sounds like you missed that configuration.  It is within the PCIe IP.

    The XDC does not have anything to do with the transceivers.  Those are hard pins that you cannot change.

    --Dan

  • 0 in reply to drozwood90

    Hi zedman2000, thank you for your reply.

    Before try to make a project for PCIe DMA endpoint, I try the PCIe PIO demo and it works. But you are talking about that the DMA endpoint will not work at all for 7015 or it's work but with lower speed?

    I need to exchange data between FPGA and PC with a slow speed (10-20 Mbit/s) can I use this IP or something else?

    For the 7030, I've only read the pdf file within the endpoint reference design zip (Zynq_MMP_PCIe_Design.pdf), and at page 9 will configure 4 lanes for PCI. Am I see the wrong reference design?

    Thanks!