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Picozed 7015 + Carrier Card + Gig SFP

Former Member

Hello All,

I'm attempting to use the Xilinx 1g/2.5g PCS/PMA to connect a Finisar SFP module in the SFP slot of the carrier card to the PS GEM1 on a Picozed 7015. My design is similar to that of xapp1082 but adapted to the picozed.

I'm using Vivado 2015.2, and a new picozed 7015 and carrier card.

The carrier card has been configured to output a 125Mhz clock (mgtrefclk1). The independent clock for the core is being provided by the PS oscillator (200MHz). Both clocks have been verified by externally connecting a scope.

I've been working on this for several weeks and am encountering a persistent issue where the transceiver GTP PLL0 fails to stay locked ONLY when the SFP is inserted in the slot.

I originally thought the core was sending a reset signal to the PLL so i implemented the PLL in the example design and removed the reset connection between the PCS/PMA and the PLL and tied it to gpio so that I could manually reset the PLL. In this configuration, I can reset the PLL and it is again stable until the SFP is inserted, at which point the PLL locked signal will begin to toggle.

I have 2 carrier cards and 2 picozeds, and this behavior is exhibited on both.

I've also got several SFP's. The finisar copper sfp's cause the pll to disconnect instantly upon being connected. (or the pll never maintains a lock if the sfp was in the slot when the board was powered on). The finisar fiber (850nm) sfp's can be inserted without disrupting the lock but will once an optical input is tied to the sfp rx port, then the lock will be lost. I have dozens of SFP's and I've connected several different ones and the behavior is the same with every one I've tried.

At this point, I'm wondering if anyone out there has managed to use the SFP port on the carrier card (I can't possibly be the first?!). I'm a computer programmer and relatively new to FPGA design and I therefore don't discount the possibility that there may be a flaw in my bitstream.

Any wisdom would be appreciated. 





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  • 0

    Hi there,

    I have personally used Finisar SFP+ modules with this carrier card for both a 7015 and 7030.  I have not seen the behavior you are seeing. 

    I think first, let's validate all of your hardware.  To validate your hardware, can you run through the IBERT design that was posted?  You can find the walk-through here:
    http://picozed.org/support/design/4701/76
    Search "IBERT Design"
    Feel free to extract the prebuilt project and run that as a QUICK validation.  I would suggest walking through the document to familiarize yourself with the IBERT tool set as it might become necessary for our troubleshooting for you to be familiar with it.

    You can also check these tech-tip videos out on how I setup and configured the board-set.
    http://picozed.org/support/trainings-and-videos
    Tech Tip - Transceiver Tools 101: Intro to IBERT
    Tech Tip - Transceiver Tools 102: We have an IBERT bit stream, now what?
    Tech Tip - Transceiver Tools 103: Now that we are running, what are all these adjustments?
    Tech Tip - Transceiver Tools 104: Getting More Margin

    This should prove that your hardware is good or not.  Please note that there is a laser ENABLE that needs to be set in order to run the SFP with the design.  The walkthrough describes what you need to change in order to set this - or use the prebuilt image.  That is the image I use in the design.

    Please let me know how that goes and then we can take the next step of figuring out the PLL locking issue.

    --Dan

Reply
  • 0

    Hi there,

    I have personally used Finisar SFP+ modules with this carrier card for both a 7015 and 7030.  I have not seen the behavior you are seeing. 

    I think first, let's validate all of your hardware.  To validate your hardware, can you run through the IBERT design that was posted?  You can find the walk-through here:
    http://picozed.org/support/design/4701/76
    Search "IBERT Design"
    Feel free to extract the prebuilt project and run that as a QUICK validation.  I would suggest walking through the document to familiarize yourself with the IBERT tool set as it might become necessary for our troubleshooting for you to be familiar with it.

    You can also check these tech-tip videos out on how I setup and configured the board-set.
    http://picozed.org/support/trainings-and-videos
    Tech Tip - Transceiver Tools 101: Intro to IBERT
    Tech Tip - Transceiver Tools 102: We have an IBERT bit stream, now what?
    Tech Tip - Transceiver Tools 103: Now that we are running, what are all these adjustments?
    Tech Tip - Transceiver Tools 104: Getting More Margin

    This should prove that your hardware is good or not.  Please note that there is a laser ENABLE that needs to be set in order to run the SFP with the design.  The walkthrough describes what you need to change in order to set this - or use the prebuilt image.  That is the image I use in the design.

    Please let me know how that goes and then we can take the next step of figuring out the PLL locking issue.

    --Dan

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  • 0 in reply to drozwood90

    Hi Dan,

    OK, I spent considerable time over the last several days trying to validate the hardware and I'm getting strange results.

    Firstly, I followed the ibert video's you made step by step including altering my board config to a 250 mhz clock. I only have the SFP+ loopback (no sma cables, fmc or pcie at this time) my output is the same as yours with the following differences: I'm now using 2015.3 (was using 2015.2 before) and a xilinx platform cable usb 2 once I get to autodetect serial links screen, my Vivado detects none.

    Then it gets goofy. I have 2 carrier cards and 2 7015's. The first card with pll/xcvrs configured as per your video will not connect - all xcvrs in near-end pma loopback, pll locked, but no link. Multiple attempts at reset fail to allow the device to link.

    Now the second board:

    If I configure it for internal loopback (near-end pma), i can get all channels to lock if the sma loopback adapter isn't in the slot... I let it run for 10 minutes or so without bit errors in internal loopback but once I plug in the sfp loopback adapter, the links go down and I can't get the internal near-end pma loopback to stay linked and error free on all 4 channels at once (certain reset combinations will land me with 0 and 1 connecting 2 and 3 no link etc..). Removing the sma loopback plug returns the internal loopback to functional state on all 4 channels.

    Then it gets seriously voodoo -- If, using hardware manager, I configure the gtp common to use GTREFCLK0 as the clock source for PLL0, the pll again returns to lock, but all loopbacks work instantly (@3.111 ghz). zero bit errors. I remove the internal loopback from the SFP and, again, I get zero bit errors going through the actual sfp loopback. As a sanity check, I remove the sfp loopback plug to confirm that mgt2 goes down - it does - reinstall it - link comes back instantly. This behavior is identical on both of my carriercard/picozed combinations. (i did also try swapping a picozed to the other carrier card to see if perhaps I had a working combination but they both behave similarly).

    I double checked the schematic and every piece of documentation I can find and there MGT_REFCLK0 is clearly  connected to the ICS874003 jitter attenuator... I'm presuming that the VCO in this device still outputs a stable clock in the absence of an input clock signal?

    I seem to be unable to get an error free loopback when the PLL0 is connected to MGT_REFCLK1(gtrefclk1) when an sfp is in the slot. In my design(where i was using a 125 mhz configuration), the pll would not stay locked when sfp's were in place (as mentioned) - This is not the behavior I usually see in the ibert (though its done it to me once or twice on REFCLK1 - REFCLK0 seems bulletproof but its obviously not properly clocked)

    On both boards, changing the pattern from prbs 7 to 31 bits and resetting causes the refclk1 clocked transceivers, in internal loopback, to disconnect constantly and have many errors. Setting to refclk0 and 31-bit still leads to zero bit errors, even when looped back externally through the sfp.

    I ordered a picozed 7030 yesterday. At this point I'm assuming that ibert is probably nearly impossible to mess up given its simplicity and that the issue I'm seeing points to some type of hardware issue with the CDCM61002 or wiring/power to/from it... I did buy both carrier cards and both picozeds in the same order at the end of June.

    Also note that I bought an loopback sfp+ to ensure that the laser on signal didn't play into any of my tests. I had to hack up the edit the earlier ibert example when using a 850nm sfp but it doesn't seem to be required for my loopback (which is probably just looped on the pcb)

    Your insight is appreciated.