Hello All,
I'm attempting to use the Xilinx 1g/2.5g PCS/PMA to connect a Finisar SFP module in the SFP slot of the carrier card to the PS GEM1 on a Picozed 7015. My design is similar to that of xapp1082 but adapted to the picozed.
I'm using Vivado 2015.2, and a new picozed 7015 and carrier card.
The carrier card has been configured to output a 125Mhz clock (mgtrefclk1). The independent clock for the core is being provided by the PS oscillator (200MHz). Both clocks have been verified by externally connecting a scope.
I've been working on this for several weeks and am encountering a persistent issue where the transceiver GTP PLL0 fails to stay locked ONLY when the SFP is inserted in the slot.
I originally thought the core was sending a reset signal to the PLL so i implemented the PLL in the example design and removed the reset connection between the PCS/PMA and the PLL and tied it to gpio so that I could manually reset the PLL. In this configuration, I can reset the PLL and it is again stable until the SFP is inserted, at which point the PLL locked signal will begin to toggle.
I have 2 carrier cards and 2 picozeds, and this behavior is exhibited on both.
I've also got several SFP's. The finisar copper sfp's cause the pll to disconnect instantly upon being connected. (or the pll never maintains a lock if the sfp was in the slot when the board was powered on). The finisar fiber (850nm) sfp's can be inserted without disrupting the lock but will once an optical input is tied to the sfp rx port, then the lock will be lost. I have dozens of SFP's and I've connected several different ones and the behavior is the same with every one I've tried.
At this point, I'm wondering if anyone out there has managed to use the SFP port on the carrier card (I can't possibly be the first?!). I'm a computer programmer and relatively new to FPGA design and I therefore don't discount the possibility that there may be a flaw in my bitstream.
Any wisdom would be appreciated.
