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picoZed Zynq 7030 PCIe Root Complex -- Intermittent Boot Hang

jgoglio

Hello Everyone,

 

I'm going to keep this as simple as possible to start and we can elaborate as we go if necessary.

 

I'm using a picozed with Zynq 7030 with a custom carrier. That carrier allows me to boot from either a uSD or PCIe device.

On the Zynq PL, I am coding in the PCIe root complex (as in this tutorial) with Vivado 2016.1.

Now, the issue I'm encountering is an intermittent boot hang (perhaps once every ~5 boots). This hang occurs right as U-Boot is handing off to the linux kernel (boot screen says "Starting kernel...").

An interesting twist: The boot hang only occurs when the root complex code is on the FPGA. It NEVER occurs when that code is removed. In the former case, it does not matter whether I boot from the uSD or PCIe! Additionally, on a successful boot (uSD in this case) an lspci command gives me: 

# lspci 00:00.0 PCI bridge: Xilinx Corporation Device 7111

which looks normal.

 

So my question is as follows:

  1.   Does anyone know of an issue with the AXI MM PCIe IP, the Zynq7030, or picozed board that might cause this issue?
  2.   Absent that, does anyone have any advice on how to proceed? I'm already thinking of Chipscope or a Vivado upgrade. Any advice on where to look with Chipscope?

 

Thank you all in advance!

  • 0

    Hi there,

    1. I am not aware of any issues and have reset my development PC many times using the Avnet PCIe Endpoint and PCIe PIO designs without seeing any hangs or other issues using a PicoZed 7015, 7030, with FMCv1 and FMCv2 Carrier Cards.

    2. If your carrier can handle it, I would recommend trying one of the Avnet designs to see if your board hangs, in order to try to isolate the hardware / software configuration.  The Avnet designs were designed for use with the PicoZed FMC carrier cards, so make adjustments as necessary for your custom board and if you have one - use the FMCv2 carrier card to isolate SOM/Carrier Card issue.  If you are getting glitches in the clock or need clock attenuation, for other reasons, it is possible this would cause funny behavior.  Also, poor constraints would also cause strange behavior as you would end up mis-latching data at incorrect times.

    Aside from that, I would suggest you ask this question to the Xilinx forum community as it seems that this could be an issue with how you have your design configured which is based on their tutorial.  They would be the best group to help you with that.
    Here is a link to their PCIe forum:
    https://forums.xilinx.com/t5/PCI-Express/bd-p/PCIe

    --Dan