I'm going to keep this as simple as possible to start and we can elaborate as we go if necessary.
I'm using a picozed with Zynq 7030 with a custom carrier. That carrier allows me to boot from either a uSD or PCIe device.
On the Zynq PL, I am coding in the PCIe root complex (as in this tutorial) with Vivado 2016.1.
Now, the issue I'm encountering is an intermittent boot hang (perhaps once every ~5 boots). This hang occurs right as U-Boot is handing off to the linux kernel (boot screen says "Starting kernel...").
An interesting twist: The boot hang only occurs when the root complex code is on the FPGA. It NEVER occurs when that code is removed. In the former case, it does not matter whether I boot from the uSD or PCIe! Additionally, on a successful boot (uSD in this case) an lspci command gives me:
# lspci 00:00.0 PCI bridge: Xilinx Corporation Device 7111
which looks normal.
So my question is as follows:
- Does anyone know of an issue with the AXI MM PCIe IP, the Zynq7030, or picozed board that might cause this issue?
- Absent that, does anyone have any advice on how to proceed? I'm already thinking of Chipscope or a Vivado upgrade. Any advice on where to look with Chipscope?
Thank you all in advance!